119 lines
4.8 KiB
C
119 lines
4.8 KiB
C
/* FIXME: Only this does work for u-boot... find out why... [RS] */
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#if 1
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# undef io_p2v
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# undef __REG
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# ifndef __ASSEMBLY__
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# define io_p2v(PhAdd) (PhAdd)
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# define __REG(x) (*((volatile u32 *)io_p2v(x)))
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# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
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# else
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# define __REG(x) (x)
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# endif
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#endif /* UBOOT_REG_FIX */
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#define RT2880_CHIP_REG_CFG_BASE (RALINK_SYSCTL_BASE)
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//#define RT2880_CHIP_REG_CFG_BASE (0x00300000)
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/*
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* UART registers
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*/
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#define RT2880_UART1 0x0500
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#define RT2880_UART2 0x0C00 /* UART Lite */
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#define CFG_RT2880_CONSOLE RT2880_UART2 /* we use UART Lite for console */
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#define RT2880_UART_CFG_BASE (RT2880_CHIP_REG_CFG_BASE)
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#define RT2880_UART_RBR_OFFSET 0x00
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#define RT2880_UART_TBR_OFFSET 0x04
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#define RT2880_UART_IER_OFFSET 0x08
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#define RT2880_UART_IIR_OFFSET 0x0C
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#define RT2880_UART_FCR_OFFSET 0x10
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#define RT2880_UART_LCR_OFFSET 0x14
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#define RT2880_UART_MCR_OFFSET 0x18
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#define RT2880_UART_LSR_OFFSET 0x1C
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#define RT2880_UART_DLL_OFFSET 0x28
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#define RBR(x) __REG(RT2880_UART_CFG_BASE+(x)+RT2880_UART_RBR_OFFSET)
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#define TBR(x) __REG(RT2880_UART_CFG_BASE+(x)+RT2880_UART_TBR_OFFSET)
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#define IER(x) __REG(RT2880_UART_CFG_BASE+(x)+RT2880_UART_IER_OFFSET)
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#define IIR(x) __REG(RT2880_UART_CFG_BASE+(x)+RT2880_UART_IIR_OFFSET)
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#define FCR(x) __REG(RT2880_UART_CFG_BASE+(x)+RT2880_UART_FCR_OFFSET)
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#define LCR(x) __REG(RT2880_UART_CFG_BASE+(x)+RT2880_UART_LCR_OFFSET)
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#define MCR(x) __REG(RT2880_UART_CFG_BASE+(x)+RT2880_UART_MCR_OFFSET)
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#define LSR(x) __REG(RT2880_UART_CFG_BASE+(x)+RT2880_UART_LSR_OFFSET)
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#define DLL(x) __REG(RT2880_UART_CFG_BASE+(x)+RT2880_UART_DLL_OFFSET)
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#define IER_ELSI (1 << 2) /* Receiver Line Status Interrupt Enable */
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#define IER_ETBEI (1 << 1) /* Transmit Buffer Empty Interrupt Enable */
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#define IER_ERBFI (1 << 0) /* Data Ready or Character Time-Out Interrupt Enable */
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#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
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#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
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#define IIR_IID3 (1 << 3) /* Interrupt Source Encoded */
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#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
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#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
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#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
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#define FCR_RXTRIG1 (1 << 7) /* Receiver Interrupt Trigger Level */
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#define FCR_RXTRIG0 (1 << 6) /* Receiver Interrupt Trigger Level */
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#define FCR_TXTRIG1 (1 << 5) /* Transmitter Interrupt Trigger Level */
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#define FCR_TXTRIG0 (1 << 4) /* Transmitter Interrupt Trigger Level */
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#define FCR_DMAMODE (1 << 3) /* Enable DMA transfers */
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#define FCR_TXRST (1 << 2) /* Reset Transmitter FIFO */
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#define FCR_RXRST (1 << 1) /* Reset Receiver FIFO */
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#define FCR_FIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
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#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
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#define LCR_SB (1 << 6) /* Set Break */
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#define LCR_STKYP (1 << 5) /* Sticky Parity */
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#define LCR_EPS (1 << 4) /* Even Parity Select */
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#define LCR_PEN (1 << 3) /* Parity Enable */
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#define LCR_STB (1 << 2) /* Stop Bit */
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#define LCR_WLS1 (1 << 1) /* Word Length Select */
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#define LCR_WLS0 (1 << 0) /* Word Length Select */
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#define MCR_LOOP (1 << 4) /* Loop-back Mode Enable */
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#define MSR_DCD (1 << 7) /* Data Carrier Detect */
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#define MSR_RI (1 << 6) /* Ring Indicator */
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#define MSR_DSR (1 << 5) /* Data Set Ready */
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#define MSR_CTS (1 << 4) /* Clear To Send */
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#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
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#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
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#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
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#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
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#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
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#define LSR_TEMT (1 << 6) /* Transmitter Empty */
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#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
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#define LSR_BI (1 << 4) /* Break Interrupt */
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#define LSR_FE (1 << 3) /* Framing Error */
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#define LSR_PE (1 << 2) /* Parity Error */
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#define LSR_OE (1 << 1) /* Overrun Error */
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#define LSR_DR (1 << 0) /* Data Ready */
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#if defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD)
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#define CR_UART_RBR (0x00+RALINK_UART_LITE_BASE)
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#define CR_UART_THR (0x00+RALINK_UART_LITE_BASE)
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#define CR_UART_IER (0x04+RALINK_UART_LITE_BASE)
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#define CR_UART_IIR (0x08+RALINK_UART_LITE_BASE)
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#define CR_UART_FCR (0x08+RALINK_UART_LITE_BASE)
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#define CR_UART_LCR (0x0c+RALINK_UART_LITE_BASE)
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#define CR_UART_MCR (0x10+RALINK_UART_LITE_BASE)
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#define CR_UART_LSR (0x14+RALINK_UART_LITE_BASE)
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#define CR_UART_MSR (0x18+RALINK_UART_LITE_BASE)
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#define CR_UART_SCR (0x1c+RALINK_UART_LITE_BASE)
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#define CR_UART_BRDL (0x00+RALINK_UART_LITE_BASE)
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#define CR_UART_BRDH (0x04+RALINK_UART_LITE_BASE)
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#define CR_UART_WORDA (0x20+RALINK_UART_LITE_BASE)
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#define CR_UART_HWORDA (0x28+RALINK_UART_LITE_BASE)
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#define CR_UART_MISCC (0x24+RALINK_UART_LITE_BASE)
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#define CR_UART_XYD (0x2c+RALINK_UART_LITE_BASE)
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#endif
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