155 lines
3.7 KiB
C
155 lines
3.7 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/addrspace.h>
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#include <asm/arch/rt_mmap.h>
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//#include "LzmaDecode.h"
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//#define MAX_SDRAM_SIZE (64*1024*1024)
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//#define MIN_SDRAM_SIZE (8*1024*1024)
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#define MAX_SDRAM_SIZE (256*1024*1024)
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#define MIN_SDRAM_SIZE (8*1024*1024)
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#ifdef SDRAM_CFG_USE_16BIT
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#define MIN_RT2880_SDRAM_SIZE (16*1024*1024)
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#else
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#define MIN_RT2880_SDRAM_SIZE (32*1024*1024)
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#endif
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phys_size_t initdram(int board_type)
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{
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ulong size, max_size = MAX_SDRAM_SIZE;
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ulong our_address;
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asm volatile ("move %0, $25" : "=r" (our_address) :);
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/* Can't probe for RAM size unless we are running from Flash.
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*/
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#if 0
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#if defined(CFG_RUN_CODE_IN_RAM)
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printf("\n In RAM run \n");
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return MIN_SDRAM_SIZE;
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#else
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printf("\n In FLASH run \n");
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return MIN_RT2880_SDRAM_SIZE;
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#endif
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#endif
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#if defined (RT2880_FPGA_BOARD) || defined (RT2880_ASIC_BOARD)
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if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1))
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{
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//return MIN_SDRAM_SIZE;
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//fixed to 32MB
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printf("\n In RAM run \n");
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return MIN_SDRAM_SIZE;
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}
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#endif
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size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE, MAX_SDRAM_SIZE);
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if (size > max_size)
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{
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max_size = size;
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// printf("\n Return MAX size!! \n");
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return max_size;
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}
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// printf("\n Return Real size =%d !! \n",size);
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return size;
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}
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int checkboard (void)
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{
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puts ("Board: Ralink APSoC\n");
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return 0;
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}
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#if defined (RT6855A_ASIC_BOARD) || defined(RT6855A_FPGA_BOARD)
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static int watchdog_reset(void)
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{
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unsigned int word;
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//unsigned int i;
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/* check if do watch dog reset */
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if ((RALINK_REG(RALINK_HIR_REG) & 0xffff0000) == 0x40000) {
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if (!(RALINK_REG(0xbfb00080) >> 31)) {
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/* set delay counter */
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RALINK_REG(RALINK_TIMER5_LDV) = 1000;
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/* enable watch dog timer */
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word = RALINK_REG(RALINK_TIMER_CTL);
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word |= ((1 << 5) | (1 << 25));
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RALINK_REG(RALINK_TIMER_CTL) = word;
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while(1);
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}
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}
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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#if defined (RT6855A_ASIC_BOARD) || defined(RT6855A_FPGA_BOARD)
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watchdog_reset();
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#endif
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return 0;
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}
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int board_last_init_f(void)
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{
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ulong value;
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/* reset Frame engine */
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value = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x0034));
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udelay(100);
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#if defined (RT2880_FPGA_BOARD) || defined (RT2880_ASIC_BOARD)
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value |= (1 << 18);
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#else
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//2880 -> 3052 reset Frame Engine from 18 to 21
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value |= (1 << 21);
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#endif
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*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x0034) = cpu_to_le32(value);
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#if defined (RT2880_FPGA_BOARD) || defined (RT2880_ASIC_BOARD)
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value &= ~(1 << 18);
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#else
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value &= ~(1 << 21);
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#endif
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*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x0034) = cpu_to_le32(value);
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udelay(200);
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return 0;
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}
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#ifdef CONFIG_RT2880_ETH
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extern int rt2880_eth_initialize(bd_t *bis);
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int board_eth_init(bd_t *bis)
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{
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return rt2880_eth_initialize(bis);
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}
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#endif
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