482 lines
13 KiB
C
482 lines
13 KiB
C
#include <common.h>
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#include <asm/addrspace.h>
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#include <atheros.h>
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#define ATH_MAX_DDR_SIZE (256 * 1024 * 1024)
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#define ATH_DDR_SIZE_INCR (4 * 1024 * 1024)
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void _machine_restart(void)
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{
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while (1) {
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ath_reg_wr(RST_RESET_ADDRESS, RST_RESET_FULL_CHIP_RESET_SET(1));
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}
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}
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int
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ath_ddr_find_size(void)
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{
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uint8_t *p = (uint8_t *)KSEG1, pat = 0x77;
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int i;
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#define max_i (ATH_MAX_DDR_SIZE / ATH_DDR_SIZE_INCR)
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*p = pat;
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/*
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* DDR wraps around. Write a pattern to 0x0000_0000. Write an
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* address pattern at 4M, 8M, 16M etc. and check when
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* 0x0000_0000 gets overwritten.
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*/
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for(i = 1; (i < max_i); i++) {
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*(p + i * ATH_DDR_SIZE_INCR) = (uint8_t)(i);
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if (*p != pat) {
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break;
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}
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}
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return ((i < max_i) ? (i * ATH_DDR_SIZE_INCR) : ATH_MAX_DDR_SIZE);
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}
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inline int
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ath_ram_type(uint32_t bs)
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{
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if (RST_BOOTSTRAP_DDR_SELECT_GET(bs)) {
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return ATH_MEM_DDR1;
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} else {
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return ATH_MEM_DDR2;
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}
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}
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#define CFG_DDR2_SCORPION_CAS_LATENCY 4
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#ifdef CONFIG_TB614
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# define DDR_CONFIG2_SWAP_A26_A27_VAL (0x1)
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#else
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# define DDR_CONFIG2_SWAP_A26_A27_VAL (0x0)
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#endif
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#if CFG_DDR2_SCORPION_CAS_LATENCY == 4
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#define CFG_DDR2_CONFIG_VAL DDR_CONFIG_CAS_LATENCY_MSB_SET(0x1) | \
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DDR_CONFIG_OPEN_PAGE_SET(0x1) | \
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DDR_CONFIG_CAS_LATENCY_SET(0x1) | \
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DDR_CONFIG_TMRD_SET(0xf) | \
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DDR_CONFIG_TRFC_SET(0x15) | \
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DDR_CONFIG_TRRD_SET(0x7) | \
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DDR_CONFIG_TRP_SET(0x9) | \
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DDR_CONFIG_TRCD_SET(0x9) | \
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DDR_CONFIG_TRAS_SET(0x1b)
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#define CFG_DDR2_CONFIG2_VAL DDR_CONFIG2_HALF_WIDTH_LOW_SET(0x1) | \
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DDR_CONFIG2_SWAP_A26_A27_SET(DDR_CONFIG2_SWAP_A26_A27_VAL) | \
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DDR_CONFIG2_GATE_OPEN_LATENCY_SET(0x8) | \
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DDR_CONFIG2_TWTR_SET(0x15) | \
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DDR_CONFIG2_TRTP_SET(0x9) | \
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DDR_CONFIG2_TRTW_SET(0xe) | \
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DDR_CONFIG2_TWR_SET(0x1) | \
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DDR_CONFIG2_CKE_SET(0x1) | \
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DDR_CONFIG2_CNTL_OE_EN_SET(0x1) | \
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DDR_CONFIG2_BURST_LENGTH_SET(0x8)
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#define CFG_DDR2_CONFIG3_VAL 0x0000000a
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#define CFG_DDR2_EXT_MODE_VAL 0x402
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#define CFG_DDR2_MODE_VAL_INIT 0x143
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#define CFG_DDR2_MODE_VAL 0x43
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#define CFG_DDR2_TAP_VAL 0x10
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#define CFG_DDR2_EN_TWL_VAL 0x0000167d
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#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff
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#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32 0xff
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#elif CFG_DDR2_SCORPION_CAS_LATENCY == 5
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#define CFG_DDR2_CONFIG_VAL DDR_CONFIG_CAS_LATENCY_MSB_SET(0x1) | \
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DDR_CONFIG_OPEN_PAGE_SET(0x1) | \
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DDR_CONFIG_CAS_LATENCY_SET(0x4) | \
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DDR_CONFIG_TMRD_SET(0xf) | \
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DDR_CONFIG_TRFC_SET(0x15) | \
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DDR_CONFIG_TRRD_SET(0x7) | \
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DDR_CONFIG_TRP_SET(0x9) | \
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DDR_CONFIG_TRCD_SET(0x9) | \
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DDR_CONFIG_TRAS_SET(0x1b)
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#define CFG_DDR2_CONFIG2_VAL DDR_CONFIG2_HALF_WIDTH_LOW_SET(0x1) | \
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DDR_CONFIG2_SWAP_A26_A27_SET(DDR_CONFIG2_SWAP_A26_A27_VAL) | \
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DDR_CONFIG2_GATE_OPEN_LATENCY_SET(0xb) | \
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DDR_CONFIG2_TWTR_SET(0x15) | \
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DDR_CONFIG2_TRTP_SET(0x9) | \
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DDR_CONFIG2_TRTW_SET(0xe) | \
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DDR_CONFIG2_TWR_SET(0x1) | \
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DDR_CONFIG2_CKE_SET(0x1) | \
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DDR_CONFIG2_CNTL_OE_EN_SET(0x1) | \
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DDR_CONFIG2_BURST_LENGTH_SET(0x8)
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#define CFG_DDR2_CONFIG3_VAL 0x0000000a
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#define CFG_DDR2_EXT_MODE_VAL 0x402
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#define CFG_DDR2_MODE_VAL_INIT 0x153
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#define CFG_DDR2_MODE_VAL 0x53
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#define CFG_DDR2_TAP_VAL 0x10
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#define CFG_DDR2_EN_TWL_VAL 0x00001e7d
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#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff
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#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32 0xff
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#endif
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#define CFG_DDR1_CONFIG_VAL DDR_CONFIG_OPEN_PAGE_SET(0x1) | \
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DDR_CONFIG_CAS_LATENCY_SET(0x7) | \
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DDR_CONFIG_TMRD_SET(0x5) | \
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DDR_CONFIG_TRFC_SET(0x7) | \
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DDR_CONFIG_TRRD_SET(0x4) | \
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DDR_CONFIG_TRP_SET(0x6) | \
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DDR_CONFIG_TRCD_SET(0x6) | \
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DDR_CONFIG_TRAS_SET(0x10)
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#define CFG_DDR1_CONFIG2_VAL DDR_CONFIG2_HALF_WIDTH_LOW_SET(0x1) | \
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DDR_CONFIG2_GATE_OPEN_LATENCY_SET(0x6) | \
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DDR_CONFIG2_TWTR_SET(0xe) | \
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DDR_CONFIG2_TRTP_SET(0x8) | \
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DDR_CONFIG2_TRTW_SET(0xe) | \
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DDR_CONFIG2_TWR_SET(0xd) | \
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DDR_CONFIG2_CKE_SET(0x1) | \
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DDR_CONFIG2_CNTL_OE_EN_SET(0x1) | \
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DDR_CONFIG2_BURST_LENGTH_SET(0x8)
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#define CFG_DDR1_CONFIG3_VAL 0x0
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#define CFG_DDR1_EXT_MODE_VAL 0x0
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#define CFG_DDR1_MODE_VAL_INIT 0x133
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#define CFG_DDR1_MODE_VAL 0x33
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#define CFG_DDR1_RD_DATA_THIS_CYCLE_VAL_16 0xffff
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#define CFG_DDR1_RD_DATA_THIS_CYCLE_VAL_32 0xff
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#define CFG_DDR1_TAP_VAL 0x20
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#define CFG_DDR_CTL_CONFIG DDR_CTL_CONFIG_SRAM_TSEL_SET(0x1) | \
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DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(0x1) | \
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DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(0x1) | \
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DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(0x1) | \
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DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(0x1) | \
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DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(0x1) | \
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DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_SET(0x1) | \
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DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_SET(0x1)
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int /* ram type */
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ath_ddr_initial_config(uint32_t refresh)
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{
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#if !defined(CONFIG_ATH_NAND_BR) && !defined(CONFIG_ATH_EMULATION)
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int ddr_config, ddr_config2, ddr_config3, ext_mod, mod_val,
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mod_val_init, cycle_val, tap_val, type, ctl_config;
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uint32_t *pll = (unsigned *)PLL_CONFIG_VAL_F;
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uint32_t bootstrap;
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// prmsg("\nsri\n");
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// prmsg("Scorpion 1.%d\n", ath_reg_rd(RST_REVISION_ID_ADDRESS) & 0xf);
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bootstrap = ath_reg_rd(RST_BOOTSTRAP_ADDRESS);
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switch(type = ath_ram_type(bootstrap)) {
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case ATH_MEM_DDR2:
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ddr_config = CFG_DDR2_CONFIG_VAL;
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ddr_config2 = CFG_DDR2_CONFIG2_VAL;
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ddr_config3 = CFG_DDR2_CONFIG3_VAL;
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ext_mod = CFG_DDR2_EXT_MODE_VAL;
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mod_val_init = CFG_DDR2_MODE_VAL_INIT;
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mod_val = CFG_DDR2_MODE_VAL;
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tap_val = CFG_DDR2_TAP_VAL;
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ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x10);
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udelay(10);
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ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x20);
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udelay(10);
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//prmsg("%s(%d): (", __func__, __LINE__);
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if (RST_BOOTSTRAP_DDR_WIDTH_GET(bootstrap)) {
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prmsg("32");
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ctl_config = CFG_DDR_CTL_CONFIG |
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DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(0x1);
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cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32;
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} else {
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prmsg("16");
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ctl_config = CFG_DDR_CTL_CONFIG |
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DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(0x1) |
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DDR_CTL_CONFIG_HALF_WIDTH_SET(0x1);
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cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16;
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}
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ctl_config |= CPU_DDR_SYNC_MODE;
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ath_reg_wr_nf(DDR_CTL_CONFIG_ADDRESS, ctl_config);
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prmsg("bit ddr2 ");
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udelay(10);
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break;
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case ATH_MEM_DDR1:
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ddr_config = CFG_DDR1_CONFIG_VAL;
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ddr_config2 = CFG_DDR1_CONFIG2_VAL;
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ddr_config3 = CFG_DDR1_CONFIG3_VAL;
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ext_mod = CFG_DDR1_EXT_MODE_VAL;
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mod_val_init = CFG_DDR1_MODE_VAL_INIT;
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mod_val = CFG_DDR1_MODE_VAL;
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tap_val = CFG_DDR1_TAP_VAL;
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//prmsg("%s(%d): (", __func__, __LINE__);
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if (RST_BOOTSTRAP_DDR_WIDTH_GET(bootstrap)) {
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prmsg("32");
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ctl_config = CFG_DDR_CTL_CONFIG;
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cycle_val = CFG_DDR1_RD_DATA_THIS_CYCLE_VAL_32;
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} else {
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prmsg("16");
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cycle_val = CFG_DDR1_RD_DATA_THIS_CYCLE_VAL_16;
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ctl_config = 0;
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}
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ctl_config |= CPU_DDR_SYNC_MODE;
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ath_reg_wr_nf(DDR_CTL_CONFIG_ADDRESS, ctl_config);
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udelay(10);
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prmsg("bit) ddr1\n");
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break;
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}
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#if 0
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if (*pll == PLL_MAGIC) {
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uint32_t cas = pll[5];
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if (cas == 3 || cas == 4) {
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cas = (cas * 2) + 2;
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ddr_config &= ~(DDR_CONFIG_CAS_LATENCY_MSB_MASK |
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DDR_CONFIG_CAS_LATENCY_MASK);
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ddr_config |= DDR_CONFIG_CAS_LATENCY_SET(cas & 0x7) |
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DDR_CONFIG_CAS_LATENCY_MSB_SET((cas >> 3) & 1);
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cas = pll[5];
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ddr_config2 &= ~DDR_CONFIG2_GATE_OPEN_LATENCY_MASK;
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ddr_config2 |= DDR_CONFIG2_GATE_OPEN_LATENCY_SET((2 * cas) + 1);
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if (type == ATH_MEM_DDR2) {
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uint32_t tmp;
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tmp = ath_reg_rd(DDR2_CONFIG_ADDRESS);
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tmp &= ~DDR2_CONFIG_DDR2_TWL_MASK;
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tmp |= DDR2_CONFIG_DDR2_TWL_SET(cas == 3 ? 3 : 5);
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ath_reg_wr_nf(DDR2_CONFIG_ADDRESS, tmp);
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}
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mod_val = (cas == 3 ? 0x33 : 0x43);
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mod_val_init = 0x100 | mod_val;
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}
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}
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#endif
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ath_reg_wr_nf(DDR_RD_DATA_THIS_CYCLE_ADDRESS, cycle_val);
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udelay(100);
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ath_reg_wr_nf(DDR_BURST_ADDRESS, 0x74444444);
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udelay(100);
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ath_reg_wr_nf(DDR_BURST2_ADDRESS, 0x44444444);
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udelay(100);
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ath_reg_wr_nf(DDR_AHB_MASTER_TIMEOUT_MAX_ADDRESS, 0xfffff);
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udelay(100);
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ath_reg_wr_nf(DDR_CONFIG_ADDRESS, ddr_config);
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udelay(100);
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ath_reg_wr_nf(DDR_CONFIG2_ADDRESS, ddr_config2);
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udelay(100);
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ath_reg_wr(DDR_CONFIG_3_ADDRESS, ddr_config3);
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udelay(100);
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if (type == ATH_MEM_DDR2) {
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ath_reg_wr_nf(DDR2_CONFIG_ADDRESS, CFG_DDR2_EN_TWL_VAL);
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udelay(100);
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}
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ath_reg_wr_nf(DDR_CONFIG2_ADDRESS, ddr_config2 | 0x80); // CKE Enable
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udelay(100);
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ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x8); // Precharge
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udelay(10);
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if (type == ATH_MEM_DDR2) {
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ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x10); // EMR2
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udelay(10);
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ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x20); // EMR3
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udelay(10);
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}
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if (type == ATH_MEM_DDR1 || type == ATH_MEM_DDR2) {
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ath_reg_wr_nf(DDR_EXTENDED_MODE_REGISTER_ADDRESS, CFG_DDR2_EXT_MODE_VAL); // EMR DLL enable, Reduced Driver Impedance control, Differential DQS disabled
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udelay(100);
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ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x2); // EMR write
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udelay(10);
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}
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ath_reg_wr_nf(DDR_MODE_REGISTER_ADDRESS, mod_val_init);
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udelay(1000);
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ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x1); // MR Write
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udelay(10);
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ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x8); // Precharge
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udelay(10);
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ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x4); // Auto Refresh
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udelay(10);
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ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x4); // Auto Refresh
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udelay(10);
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// Issue MRS to remove DLL out-of-reset
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ath_reg_wr_nf(DDR_MODE_REGISTER_ADDRESS, mod_val);
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udelay(100);
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ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x1); // MR write
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udelay(100);
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if (type == ATH_MEM_DDR2) {
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ath_reg_wr_nf(DDR_EXTENDED_MODE_REGISTER_ADDRESS, 0x782);
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udelay(100);
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ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x2); // EMR write
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udelay(100);
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ath_reg_wr_nf(DDR_EXTENDED_MODE_REGISTER_ADDRESS, CFG_DDR2_EXT_MODE_VAL);
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udelay(100);
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ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x2); // EMR write
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udelay(100);
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}
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ath_reg_wr_nf(DDR_REFRESH_ADDRESS, refresh);
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udelay(100);
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ath_reg_wr(TAP_CONTROL_0_ADDRESS, tap_val);
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ath_reg_wr(TAP_CONTROL_1_ADDRESS, tap_val);
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if (RST_BOOTSTRAP_DDR_WIDTH_GET(bootstrap)) {
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ath_reg_wr (TAP_CONTROL_2_ADDRESS, tap_val);
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ath_reg_wr (TAP_CONTROL_3_ADDRESS, tap_val);
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}
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if (type == ATH_MEM_DDR2) {
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ath_reg_wr(PMU1_ADDRESS, 0x633c8176);
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// Set DDR2 Voltage to 1.8 volts
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ath_reg_wr(PMU2_ADDRESS, PMU2_LDO_TUNE_SET(3) |
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PMU2_PGM_SET(0x1));
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}
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/*
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* Based on SGMII validation for stucks, packet errors were observed and it was
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* mostly due to noise pickup on SGMII lines. Switching regulator register is to
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* be programmed with proper setting to avoid such stucks.
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*/
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ath_reg_rmw_clear(PMU1_ADDRESS, (7<<1));
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ath_reg_rmw_set(PMU1_ADDRESS, (1<<3));
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return type;
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#else // !nand flash and !emulation
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return 0;
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#endif
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}
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int
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ath_uart_freq(void)
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{
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if (ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_REF_CLK_MASK) {
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return 40 * 1000 * 1000;
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} else {
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return 25 * 1000 * 1000;
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}
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}
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#if 0
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void
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ath_sys_frequency(uint32_t *cpu, uint32_t *ddr, uint32_t *ahb)
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{
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#if !defined(CONFIG_ATH_EMULATION)
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uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl;
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#endif
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uint32_t ref;
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static uint32_t ath_cpu_freq, ath_ddr_freq, ath_ahb_freq;
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if (ath_cpu_freq)
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goto done;
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#ifdef CONFIG_ATH_EMULATION
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ath_cpu_freq = 80000000;
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ath_ddr_freq = 80000000;
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ath_ahb_freq = 40000000;
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#else
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prmsg("%s: ", __func__);
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clk_ctrl = ath_reg_rd(ATH_DDR_CLK_CTRL);
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#if 0
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pll = ath_reg_rd(CPU_DPLL2_ADDRESS);
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if (CPU_DPLL2_LOCAL_PLL_GET(pll)) {
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out_div = CPU_DPLL2_OUTDIV_GET(pll);
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pll = ath_reg_rd(CPU_DPLL_ADDRESS);
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nint = CPU_DPLL_NINT_GET(pll);
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frac = CPU_DPLL_NFRAC_GET(pll);
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ref_div = CPU_DPLL_REFDIV_GET(pll);
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|
pll = ref >> 18;
|
|
frac = frac * pll / ref_div;
|
|
prmsg("cpu srif ");
|
|
} else {
|
|
#endif
|
|
pll = ath_reg_rd(ATH_PLL_CONFIG);
|
|
out_div = CPU_PLL_CONFIG_OUTDIV_GET(pll);
|
|
ref_div = CPU_PLL_CONFIG_REFDIV_GET(pll);
|
|
nint = CPU_PLL_CONFIG_NINT_GET(pll);
|
|
frac = CPU_PLL_CONFIG_NFRAC_GET(pll);
|
|
pll = ref >> 6;
|
|
frac = frac * pll / ref_div;
|
|
prmsg("cpu apb ");
|
|
// }
|
|
ath_cpu_freq = (((nint * (ref / ref_div)) + frac) >> out_div) /
|
|
(CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(clk_ctrl) + 1);
|
|
|
|
#if 0
|
|
pll = ath_reg_rd(DDR_DPLL2_ADDRESS);
|
|
if (DDR_DPLL2_LOCAL_PLL_GET(pll)) {
|
|
out_div = DDR_DPLL2_OUTDIV_GET(pll);
|
|
|
|
pll = ath_reg_rd(DDR_DPLL_ADDRESS);
|
|
nint = DDR_DPLL_NINT_GET(pll);
|
|
frac = DDR_DPLL_NFRAC_GET(pll);
|
|
ref_div = DDR_DPLL_REFDIV_GET(pll);
|
|
pll = ref >> 18;
|
|
frac = frac * pll / ref_div;
|
|
prmsg("ddr srif ");
|
|
} else {
|
|
#endif
|
|
pll = ath_reg_rd(ATH_DDR_PLL_CONFIG);
|
|
out_div = DDR_PLL_CONFIG_OUTDIV_GET(pll);
|
|
ref_div = DDR_PLL_CONFIG_REFDIV_GET(pll);
|
|
nint = DDR_PLL_CONFIG_NINT_GET(pll);
|
|
frac = DDR_PLL_CONFIG_NFRAC_GET(pll);
|
|
pll = ref >> 10;
|
|
frac = frac * pll / ref_div;
|
|
prmsg("ddr apb ");
|
|
// }
|
|
ath_ddr_freq = (((nint * (ref / ref_div)) + frac) >> out_div) /
|
|
(CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(clk_ctrl) + 1);
|
|
|
|
if (CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) {
|
|
ath_ahb_freq = ath_ddr_freq /
|
|
(CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(clk_ctrl) + 1);
|
|
} else {
|
|
ath_ahb_freq = ath_cpu_freq /
|
|
(CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(clk_ctrl) + 1);
|
|
}
|
|
#endif
|
|
ath_cpu_freq = 720 * 1000000;
|
|
ath_ddr_freq = 600 * 1000000;
|
|
ath_ahb_freq = 200 * 1000000;
|
|
prmsg("cpu %u ddr %u ahb %u\n",
|
|
ath_cpu_freq / 1000000,
|
|
ath_ddr_freq / 1000000,
|
|
ath_ahb_freq / 1000000);
|
|
done:
|
|
*cpu = ath_cpu_freq;
|
|
*ddr = ath_ddr_freq;
|
|
*ahb = ath_ahb_freq;
|
|
|
|
}
|
|
#endif
|