154 lines
4.3 KiB
ArmAsm
154 lines
4.3 KiB
ArmAsm
#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <atheros.h>
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/*
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* Helper macros.
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* These Clobber t7, t8 and t9
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*/
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#define reg_write(_reg, _val) \
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li t7, KSEG1ADDR(_reg); \
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li t8, _val; \
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sw t8, 0(t7);
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#define reg_rmw_set(_reg, _mask, _val) \
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li t7, KSEG1ADDR(_reg); \
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lw t8, 0(t7); \
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li t9, ~(_mask); \
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and t8, t8, t9; \
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li t9, _val; \
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or t8, t8, t9; \
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sw t8, 0(t7)
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#define cpu_pll_set(_mask, _val) \
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reg_rmw_set(CPU_PLL_CONFIG_ADDRESS, _mask, _val)
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#define ddr_pll_set(_mask, _val) \
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reg_rmw_set(DDR_PLL_CONFIG_ADDRESS, _mask, _val)
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#define cpu_ddr_control_set(_mask, _val) \
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reg_rmw_set(CPU_DDR_CLOCK_CONTROL_ADDRESS, _mask, _val)
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/******************************************************************************
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* first level initialization:
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*
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* 0) If clock cntrl reset switch is already set, we're recovering from
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* "divider reset"; goto 3.
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* 1) Setup divide ratios.
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* 2) Reset.
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* 3) Setup pll's, wait for lock.
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*
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*****************************************************************************/
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.globl lowlevel_init
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.type lowlevel_init, @function
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.text
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.align 4
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lowlevel_init:
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#if !defined(CONFIG_ATH_EMULATION)
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#if !defined(CONFIG_ATH_NAND_BR)
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reg_write(BB_DPLL2_ADDRESS, BB_DPLL2_KI_SET(4) | \
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BB_DPLL2_KD_SET(0x60) | \
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BB_DPLL2_PLL_PWD_SET(1) | \
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BB_DPLL2_DELTA_SET(0x1e));
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reg_write(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KI_SET(4) | \
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PCIe_DPLL2_KD_SET(0x60) | \
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PCIe_DPLL2_PLL_PWD_SET(1) | \
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PCIe_DPLL2_DELTA_SET(0x1e));
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reg_write(DDR_DPLL2_ADDRESS, DDR_DPLL2_KI_SET(4) | \
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DDR_DPLL2_KD_SET(0x60) | \
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DDR_DPLL2_PLL_PWD_SET(1) | \
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DDR_DPLL2_DELTA_SET(0x1e));
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reg_write(CPU_DPLL2_ADDRESS, CPU_DPLL2_KI_SET(4) | \
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CPU_DPLL2_KD_SET(0x60) | \
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CPU_DPLL2_PLL_PWD_SET(1) | \
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CPU_DPLL2_DELTA_SET(0x1e));
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li t5, CPU_PLL_CONFIG_NINT_VAL
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li t6, DDR_PLL_CONFIG_NINT_VAL
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li t4, CPU_PLL_DITHER_VAL
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li t3, DDR_PLL_DITHER_VAL
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li t7, PLL_CONFIG_VAL_F
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lw t8, 0(t7)
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li t7, PLL_MAGIC
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beq t7, t8, read_from_flash
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nop
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j pll_bypass_set
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nop
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read_from_flash:
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li t7, PLL_CONFIG_VAL_F + 4
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lw t5, 0(t7)
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lw t4, 4(t7)
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lw t6, 8(t7)
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lw t3, 12(t7)
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pll_bypass_set:
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cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1));
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cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1));
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cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1));
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init_cpu_pll:
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li t7, KSEG1ADDR(CPU_PLL_CONFIG_ADDRESS);
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li t8, (CPU_PLL_CONFIG_PLLPWD_SET(1) | \
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CPU_PLL_CONFIG_REF_DIV_VAL | \
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CPU_PLL_CONFIG_RANGE_VAL | \
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CPU_PLL_CONFIG_OUT_DIV_VAL1);
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or t8, t8, t5
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sw t8, 0(t7);
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init_ddr_pll:
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li t7, KSEG1ADDR(DDR_PLL_CONFIG_ADDRESS);
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li t8, (DDR_PLL_CONFIG_PLLPWD_SET(1) | \
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DDR_PLL_CONFIG_REF_DIV_VAL | \
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DDR_PLL_CONFIG_RANGE_VAL | \
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DDR_PLL_CONFIG_OUT_DIV_VAL1);
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or t8, t8, t6
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sw t8, 0(t7);
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init_ahb_pll:
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reg_write(CPU_DDR_CLOCK_CONTROL_ADDRESS,
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CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL |
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AHB_CLK_FROM_DDR |
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CPU_AND_DDR_CLK_FROM_DDR |
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CPU_AND_DDR_CLK_FROM_CPU |
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CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV |
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CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV |
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CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1) |
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CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1) |
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CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1));
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pll_pwd_unset:
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cpu_pll_set(CPU_PLL_CONFIG_PLLPWD_MASK, CPU_PLL_CONFIG_PLLPWD_SET(0));
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ddr_pll_set(DDR_PLL_CONFIG_PLLPWD_MASK, DDR_PLL_CONFIG_PLLPWD_SET(0));
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outdiv_unset:
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cpu_pll_set(CPU_PLL_CONFIG_OUTDIV_MASK, CPU_PLL_CONFIG_OUT_DIV_VAL2);
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ddr_pll_set(DDR_PLL_CONFIG_OUTDIV_MASK, DDR_PLL_CONFIG_OUT_DIV_VAL2);
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pll_bypass_unset:
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cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(0));
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cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(0));
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cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(0));
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ddr_pll_dither_unset:
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li t7, KSEG1ADDR(DDR_PLL_DITHER_ADDRESS);
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sw t3, 0(t7);
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cpu_pll_dither_unset:
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li t7, KSEG1ADDR(CPU_PLL_DITHER_ADDRESS);
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sw t4, 0(t7);
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#endif /* !defined(CONFIG_ATH_NAND_BR) */
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#endif /* !defined(CONFIG_ATH_EMULATION) */
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jr ra
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nop
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