435 lines
12 KiB
C
435 lines
12 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include "serial.h"
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#include <asm/arch/rt_mmap.h>
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extern unsigned long mips_bus_feq;
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/* this function does not need to know the cpu and bus clock after RT3352. the clock is fix at 40Mhz */
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void serial_setbrg (void)
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{
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//DECLARE_GLOBAL_DATA_PTR;
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unsigned int clock_divisor = 0;
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u32 reg, cpu_clock __maybe_unused = 0;
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#if defined(RT2880_ASIC_BOARD) || defined(RT2883_ASIC_BOARD) || defined(RT3052_ASIC_BOARD) || defined(RT3352_ASIC_BOARD) || defined(RT3883_ASIC_BOARD) || defined (RT5350_ASIC_BOARD) || defined(RT6855_ASIC_BOARD) || defined(RT6352_ASIC_BOARD) || defined(RT71100_ASIC_BOARD)
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u8 clk_sel;
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u8 clk_sel2;
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#endif
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reg = RALINK_REG(RT2880_SYSCFG_REG);
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/*
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* CPU_CLK_SEL (bit 21:20)
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*/
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#ifdef RT2880_FPGA_BOARD
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cpu_clock = 25 * 1000 * 1000;
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mips_bus_feq = cpu_clock / 2;
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#elif defined (RT2883_FPGA_BOARD) || defined (RT3052_FPGA_BOARD) || defined (RT3352_FPGA_BOARD) || defined (RT3883_FPGA_BOARD) || defined (RT5350_FPGA_BOARD) || defined (RT6855_FPGA_BOARD) || defined(RT6352_FPGA_BOARD) || defined(RT71100_FPGA_BOARD)
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cpu_clock = 40 * 1000 * 1000;
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mips_bus_feq = cpu_clock / 3;
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#elif defined(RT2883_ASIC_BOARD)
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clk_sel = (reg>>18) & 0x03;
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switch(clk_sel) {
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case 0:
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cpu_clock = (380*1000*1000);
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break;
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case 1:
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cpu_clock = (390*1000*1000);
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break;
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case 2:
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cpu_clock = (400*1000*1000);
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break;
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case 3:
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cpu_clock = (420*1000*1000);
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break;
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}
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mips_bus_feq = cpu_clock / 3;
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#elif defined(RT3052_ASIC_BOARD)
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#if defined(RT3350_ASIC_BOARD)
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//MA10 is floating
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cpu_clock = (320*1000*1000);
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#else
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clk_sel = (reg>>18) & 0x01;
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switch(clk_sel) {
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case 0:
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cpu_clock = (320*1000*1000);
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break;
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case 1:
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cpu_clock = (384*1000*1000);
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break;
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}
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#endif
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mips_bus_feq = cpu_clock / 3;
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#elif defined(RT3352_ASIC_BOARD)
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clk_sel = (reg>>8) & 0x01;
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switch(clk_sel) {
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case 0:
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cpu_clock = (384*1000*1000);
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break;
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case 1:
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cpu_clock = (400*1000*1000);
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break;
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}
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mips_bus_feq = cpu_clock / 3;
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#elif defined(RT5350_ASIC_BOARD)
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clk_sel = (reg>>8) & 0x01;
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clk_sel2 = (reg>>10) & 0x01;
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clk_sel |= (clk_sel2 << 1 );
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switch(clk_sel) {
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case 0:
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cpu_clock = (360*1000*1000);
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mips_bus_feq = (120*1000*1000);
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break;
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case 1:
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//reserved
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break;
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case 2:
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cpu_clock = (320*1000*1000);
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mips_bus_feq = (80*1000*1000);
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break;
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case 3:
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cpu_clock = (300*1000*1000);
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mips_bus_feq = (100*1000*1000);
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break;
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}
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#elif defined(RT6855_ASIC_BOARD)
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cpu_clock = (400*1000*1000);
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mips_bus_feq = (133*1000*1000);
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#elif defined(RT6352_ASIC_BOARD)
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/*FIXME*/
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cpu_clock = (600*1000*1000);
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mips_bus_feq = (133*1000*1000);
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#elif defined(RT71100_ASIC_BOARD)
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/*FIXME*/
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cpu_clock = (800*1000*1000);
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mips_bus_feq = (133*1000*1000);
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#elif defined(RT3883_ASIC_BOARD)
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clk_sel = (reg>>8) & 0x03;
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switch(clk_sel) {
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case 0:
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cpu_clock = (250*1000*1000);
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break;
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case 1:
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cpu_clock = (384*1000*1000);
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break;
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case 2:
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cpu_clock = (480*1000*1000);
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break;
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case 3:
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cpu_clock = (500*1000*1000);
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break;
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}
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#if defined (CONFIG_ENV_IS_IN_SPI_FLASH)
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if ((reg>>17) & 0x1) { //DDR2
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switch(clk_sel) {
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case 0:
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mips_bus_feq = (125*1000*1000);
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break;
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case 1:
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mips_bus_feq = (128*1000*1000);
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break;
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case 2:
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mips_bus_feq = (160*1000*1000);
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break;
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case 3:
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mips_bus_feq = (166*1000*1000);
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break;
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}
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}
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else {
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switch(clk_sel) {
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case 0:
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mips_bus_feq = (83*1000*1000);
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break;
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case 1:
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mips_bus_feq = (96*1000*1000);
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break;
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case 2:
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mips_bus_feq = (120*1000*1000);
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break;
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case 3:
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mips_bus_feq = (125*1000*1000);
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break;
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}
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}
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#elif defined ON_BOARD_SDR
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switch(clk_sel) {
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case 0:
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mips_bus_feq = (83*1000*1000);
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break;
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case 1:
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mips_bus_feq = (96*1000*1000);
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break;
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case 2:
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mips_bus_feq = (120*1000*1000);
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break;
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case 3:
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mips_bus_feq = (125*1000*1000);
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break;
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}
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#elif defined ON_BOARD_DDR2
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switch(clk_sel) {
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case 0:
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mips_bus_feq = (125*1000*1000);
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break;
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case 1:
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mips_bus_feq = (128*1000*1000);
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break;
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case 2:
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mips_bus_feq = (160*1000*1000);
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break;
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case 3:
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mips_bus_feq = (166*1000*1000);
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break;
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}
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#else
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#error undef SDR or DDR
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#endif
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#elif defined(RT2880_ASIC_BOARD)
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clk_sel = (reg>>20) & 0x03;
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switch(clk_sel) {
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#ifdef RT2880_MP
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case 0:
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cpu_clock = (250*1000*1000);
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break;
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case 1:
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cpu_clock = (266*1000*1000);
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break;
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case 2:
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cpu_clock = (280*1000*1000);
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break;
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case 3:
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cpu_clock = (300*1000*1000);
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break;
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#else /* RT2880 SHUTTLE */
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case 0:
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cpu_clock = (233*1000*1000);
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break;
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case 1:
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cpu_clock = (250*1000*1000);
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break;
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case 2:
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cpu_clock = (266*1000*1000);
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break;
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case 3:
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cpu_clock = (280*1000*1000);
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break;
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#endif
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}
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mips_bus_feq = cpu_clock / 2;
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#elif defined(RT6855A_ASIC_BOARD) || defined(RT6855A_FPGA_BOARD)
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//use bbu_init_uart() instead, and this is to avoid the compiling error
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#else
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#error "undefined Platform"
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#endif
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//RALINK_REG(RT2880_SYSCFG_REG) = reg;
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//reset uart lite and uart full
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#if defined(RT2880_ASIC_BOARD) || defined(RT2880_FPGA_BOARD)
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*(unsigned long *)(RALINK_SYSCTL_BASE + 0x0034) = cpu_to_le32(1<<12);
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#elif defined(RT2883_ASIC_BOARD) || defined(RT2883_FPGA_BOARD) || \
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defined(RT3052_ASIC_BOARD) || defined(RT3052_FPGA_BOARD) || \
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defined(RT3352_ASIC_BOARD) || defined(RT3352_FPGA_BOARD) || \
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defined(RT5350_ASIC_BOARD) || defined(RT5350_FPGA_BOARD) || \
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defined(RT3883_ASIC_BOARD) || defined(RT3883_FPGA_BOARD) || \
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defined(RT6855_ASIC_BOARD) || defined(RT6855_FPGA_BOARD) || \
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defined(RT6352_ASIC_BOARD) || defined(RT6352_FPGA_BOARD) || \
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defined(RT71100_ASIC_BOARD) || defined(RT71100_FPGA_BOARD)
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*(unsigned long *)(RALINK_SYSCTL_BASE + 0x0034) = cpu_to_le32(1<<19|1<<12);
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#elif defined(RT6855A_ASIC_BOARD) || defined(RT6855A_FPGA_BOARD)
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//use bbu_init_uart insead and avoid the compiling error
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#else
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#error "undefined Platform"
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#endif
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/* RST Control change from W1C to W1W0 to reset, update 20080812 */
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*(unsigned long *)(RALINK_SYSCTL_BASE + 0x0034) = 0;
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//clock_divisor = (CPU_CLOCK_RATE / SERIAL_CLOCK_DIVISOR / gd->baudrate);
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#if defined(RT3883_ASIC_BOARD) || defined(RT3883_FPGA_BOARD) || \
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defined(RT3352_ASIC_BOARD) || defined(RT3352_FPGA_BOARD) || \
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defined(RT5350_ASIC_BOARD) || defined(RT5350_FPGA_BOARD) || \
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defined(RT6855_ASIC_BOARD) || defined(RT6855_FPGA_BOARD) || \
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defined(RT6352_ASIC_BOARD) || defined(RT6352_FPGA_BOARD) || \
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defined(RT71100_ASIC_BOARD) || defined(RT71100_FPGA_BOARD)
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clock_divisor = (40*1000*1000/ SERIAL_CLOCK_DIVISOR / CONFIG_BAUDRATE);
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#else
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clock_divisor = (mips_bus_feq/ SERIAL_CLOCK_DIVISOR / CONFIG_BAUDRATE);
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#endif
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IER(CFG_RT2880_CONSOLE) = 0; /* Disable for now */
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FCR(CFG_RT2880_CONSOLE) = 0; /* No fifos enabled */
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/* set baud rate */
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LCR(CFG_RT2880_CONSOLE) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
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DLL(CFG_RT2880_CONSOLE) = clock_divisor & 0xffff;
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LCR(CFG_RT2880_CONSOLE) = LCR_WLS0 | LCR_WLS1;
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}
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#if 0
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static unsigned long uclk_20M[13]={ // 65000*(b*16*1)/2000000
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59904, // Baud rate 115200
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29952, // Baud rate 57600
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19968, // Baud rate 38400
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14976, // Baud rate 28800
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9984, // Baud rate 19200
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7488, // Baud rate 14400
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4992, // Baud rate 9600
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2496, // Baud rate 4800
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1248, // Baud rate 2400
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624, // Baud rate 1200
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312, // Baud rate 600
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156, // Baud rate 300
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57 // Baud rate 110
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};
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#endif
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#if defined(RT6855A_ASIC_BOARD) || defined(RT6855A_FPGA_BOARD)
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void bbu_uart_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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//int i;
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unsigned long div_x, div_y;
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unsigned long word;
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int baudrate;
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if ( gd->baudrate <= 0 ) {
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baudrate = CONFIG_BAUDRATE;
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}
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// Set FIFO controo enable, reset RFIFO, TFIFO, 16550 mode, watermark=0x00 (1 byte)
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ra_outb(CR_UART_FCR, (0x0f|(0x0<<6)));
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// Set modem control to 0
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ra_outb(CR_UART_MCR, 0x0);
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// Disable IRDA, Disable Power Saving Mode, RTS , CTS flow control
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ra_outb(CR_UART_MISCC, 0x0);
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// Set interrupt Enable to, enable Tx, Rx and Line status
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/*ra_outb(CR_UART_IER, 0x01);*/
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/* access the bardrate divider */
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ra_outb(CR_UART_LCR, LCR_DLAB);
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div_y = 65000;
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div_x = 65*(baudrate*16*1)/2000;
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// div_x = uclk_20M[1];
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word = (div_x<<16)|div_y;
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ra_outl(CR_UART_XYD, word);
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/* Set Baud Rate Divisor to 1*16 */
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ra_outb(CR_UART_BRDL, 0x01);
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ra_outb(CR_UART_BRDH, 0x00);
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/* Set DLAB = 0, clength = 8, stop =1, no parity check */
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ra_outb(CR_UART_LCR, LCR_WLS0 | LCR_WLS1);
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}
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#endif
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/*
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*
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*/
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int serial_init (void)
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{
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#if defined(RT6855A_ASIC_BOARD) || defined(RT6855A_FPGA_BOARD)
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bbu_uart_init();
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#else
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serial_setbrg ();
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#endif
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return (0);
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}
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/*
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* Output a single byte to the serial port.
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*/
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void serial_putc (const char c)
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{
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#if defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD)
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while (!(ra_inb(CR_UART_LSR) & LSR_TEMT));
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ra_outb(CR_UART_THR, c);
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if (c == '\n')
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serial_putc ('\r');
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#else
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/* wait for room in the tx FIFO on UART */
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while ((LSR(CFG_RT2880_CONSOLE) & LSR_TEMT) == 0);
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TBR(CFG_RT2880_CONSOLE) = c;
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/* If \n, also do \r */
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if (c == '\n')
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serial_putc ('\r');
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#endif
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}
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/*
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* Read a single byte from the serial port. Returns 1 on success, 0
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* otherwise. When the function is succesfull, the character read is
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* written into its argument c.
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*/
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int serial_tstc (void)
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{
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#if defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD)
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return (ra_inb(CR_UART_LSR) & LSR_DR);
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#else
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return LSR(CFG_RT2880_CONSOLE) & LSR_DR;
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#endif
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}
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/*
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* Read a single byte from the serial port. Returns 1 on success, 0
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* otherwise. When the function is succesfull, the character read is
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* written into its argument c.
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*/
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int serial_getc (void)
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{
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#if defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD)
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while (!(ra_inb(CR_UART_LSR) & LSR_DR));
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return (char) (ra_inb(CR_UART_RBR) & 0xff);
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#else
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while (!(LSR(CFG_RT2880_CONSOLE) & LSR_DR));
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return (char) RBR(CFG_RT2880_CONSOLE) & 0xff;
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#endif
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}
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void
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serial_puts (const char *s)
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{
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while (*s) {
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serial_putc (*s++);
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}
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}
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