217 lines
5.9 KiB
C
Executable File
217 lines
5.9 KiB
C
Executable File
/*
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***************************************************************************
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* Ralink Tech Inc.
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* 5F., No.36, Taiyuan St., Jhubei City,
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* Hsinchu County 302,
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* Taiwan, R.O.C.
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*
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* (c) Copyright, Ralink Technology, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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***************************************************************************
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*/
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#ifndef GDMA_H
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#define GDMA_H
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/*
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* DEFINITIONS AND MACROS
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*/
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#if 0
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#define MOD_VERSION "0.4"
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#if defined (CONFIG_RALINK_RT3052)
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#define MAX_GDMA_CHANNEL 8
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#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352)
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#define MAX_GDMA_CHANNEL 16
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#else
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#error Please Choose System Type
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#endif
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#endif
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#define RALINK_GDMA_BASE (0xbfb30000)
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#define RALINK_GDMA_CTRL_BASE (RALINK_GDMA_BASE)
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#if 0
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#if defined (CONFIG_RALINK_RT3052)
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#define RALINK_GDMAISTS (RALINK_GDMA_BASE + 0x80)
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#define RALINK_GDMAGCT (RALINK_GDMA_BASE + 0x88)
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#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352)
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#define RALINK_GDMA_UNMASKINT (RALINK_GDMA_BASE + 0x200)
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#define RALINK_GDMA_DONEINT (RALINK_GDMA_BASE + 0x204)
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#define RALINK_GDMA_GCT (RALINK_GDMA_BASE + 0x220)
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#endif
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#endif
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// frank added
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#define RALINK_GDMAISTS (RALINK_GDMA_BASE + 0x0)
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#define RALINK_GDMAGCT (RALINK_GDMA_BASE + 0x8)
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#define RALINK_GDMA_UNMASKINT (RALINK_GDMA_BASE + 0x200)
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#define RALINK_GDMA_DONEINT (RALINK_GDMA_BASE + 0x204)
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#define RALINK_GDMA_GCT (RALINK_GDMA_BASE + 0x220)
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#if 0
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#define GDMA_READ_REG(addr) le32_to_cpu(*(volatile u32 *)(addr))
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#define GDMA_WRITE_REG(addr, val) *((volatile uint32_t *)(addr)) = cpu_to_le32(val)
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#define GET_GDMA_IP_VER (GDMA_READ_REG(RALINK_GDMA_GCT) & 0x6) >> 1 //GDMA_GCT[2:1]
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#endif
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#define GDMA_READ_REG(addr) (*(volatile u32 *)(addr))
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#define GDMA_WRITE_REG(addr, val) *((volatile uint32_t *)(addr)) = (val)
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#if 0
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#define RALINK_IRQ_ADDR RALINK_INTCL_BASE
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#define RALINK_REG_INTENA (RALINK_IRQ_ADDR + 0x34)
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#define RALINK_REG_INTDIS (RALINK_IRQ_ADDR + 0x38)
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#endif
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/*
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* 12bytes=GDMA Channel n Source Address(4) +
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* GDMA Channel n Destination Address(4) +
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* GDMA Channel n Control Register(4)
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*
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*/
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#define GDMA_SRC_REG(ch) (RALINK_GDMA_BASE + ch*16)
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#define GDMA_DST_REG(ch) (GDMA_SRC_REG(ch) + 4)
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#define GDMA_CTRL_REG(ch) (GDMA_DST_REG(ch) + 4)
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#define GDMA_CTRL_REG1(ch) (GDMA_CTRL_REG(ch) + 4)
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//GDMA Interrupt Status Register
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#if 0
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#if defined (CONFIG_RALINK_RT3052)
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#define UNMASK_INT_STATUS(ch) (ch+16)
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#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352)
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#define UNMASK_INT_STATUS(ch) (ch)
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#endif
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#define TXDONE_INT_STATUS(ch) (ch)
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#endif
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//Control Reg0
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#define MODE_SEL_OFFSET 0
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#define CH_EBL_OFFSET 1
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#define CH_DONEINT_EBL_OFFSET 2
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#define BRST_SIZE_OFFSET 3
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#define DST_BRST_MODE_OFFSET 6
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#define SRC_BRST_MODE_OFFSET 7
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#define TRANS_CNT_OFFSET 16
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//Control Reg1
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#if 0
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#if defined (CONFIG_RALINK_RT3052)
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#define CH_UNMASKINT_EBL_OFFSET 4
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#define NEXT_UNMASK_CH_OFFSET 1
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#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352)
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#define CH_UNMASKINT_EBL_OFFSET 1
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#define NEXT_UNMASK_CH_OFFSET 3
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#endif
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#endif
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#define COHERENT_INT_EBL_OFFSET 2
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#define CH_MASK_OFFSET 0
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// frank added
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#define NEXT_UNMASK_CH_OFFSET 3
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#if 0
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#if defined (CONFIG_RALINK_RT3052)
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//Control Reg0
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#define DST_DMA_REQ_OFFSET 8
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#define SRC_DMA_REQ_OFFSET 12
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#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352)
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//Control Reg1
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#define DST_DMA_REQ_OFFSET 8
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#define SRC_DMA_REQ_OFFSET 16
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#endif
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#endif
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#define DST_DMA_REQ_OFFSET 8
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#define SRC_DMA_REQ_OFFSET 16
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//#define GDMA_DEBUG
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#ifdef GDMA_DEBUG
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#define GDMA_PRINT(fmt, args...) printk(KERN_INFO "GDMA: " fmt, ## args)
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#else
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#define GDMA_PRINT(fmt, args...) { }
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#endif
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/*
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* TYPEDEFS AND STRUCTURES
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*/
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enum GdmaBusterMode {
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INC_MODE=0,
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FIX_MODE=1
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};
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enum GdmaBusterSize {
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BUSTER_SIZE_4B=0, /* 1 transfer */
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BUSTER_SIZE_8B=1, /* 2 transfer */
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BUSTER_SIZE_16B=2, /* 4 transfer */
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BUSTER_SIZE_32B=3, /* 8 transfer */
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BUSTER_SIZE_64B=4 /* 16 transfer */
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};
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enum GdmaDmaReqNum {
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DMA_NAND_REQ=0,
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DMA_REQ1=1,
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DMA_REQ2=2,
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DMA_REQ3=3,
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DMA_REQ4=4,
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DMA_REQ5=5,
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DMA_REQ6=6,
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DMA_REQ7=7,
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DMA_REQ8=8,
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DMA_REQ9=9,
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DMA_REQ10=10,
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DMA_REQ11=11,
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DMA_REQ12=12,
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DMA_REQ13=13,
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DMA_REQ14=14,
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DMA_REQ15=15,
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DMA_MEM_REQ=32
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};
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#define BURST_SIZE_4B 0 /* 1 transfer */
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#define BURST_SIZE_8B 1 /* 2 transfer */
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#define BURST_SIZE_16B 2 /* 4 transfer */
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#define BURST_SIZE_32B 3 /* 8 transfer */
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#define BURST_SIZE_64B 4 /* 16 transfer */
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#define SW_MODE 1
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#define HW_MODE 0
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#define DMA_REQMEM 0x20
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#define TRN_FIX 1
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#define TRN_INC 0
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int _ra_nand_prepare_dma_pull(unsigned long dst, int len);
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int _ra_nand_dma_pull(unsigned long dst, int len);
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int _ra_nand_dma_push(unsigned long src, int len);
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#endif
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