410 lines
8.6 KiB
C
Executable File
410 lines
8.6 KiB
C
Executable File
/*
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* MIPS SPRAM support
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Copyright (C) 2007, 2008 MIPS Technologies, Inc.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/ptrace.h>
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#include <linux/stddef.h>
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#include <linux/module.h>
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#include <asm/cpu.h>
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//#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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//#include <asm/r4kcache.h>
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//#include <asm/hazards.h>
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#include <asm/tc3162.h>
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#define MIPS34K_Index_Store_Data_I 0x0c
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/*
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* Cache Operations available on all MIPS processors with R4000-style caches
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*/
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#define Index_Invalidate_I 0x00
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#define Index_Writeback_Inv_D 0x01
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#define Index_Load_Tag_I 0x04
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#define Index_Load_Tag_D 0x05
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#define Index_Store_Tag_I 0x08
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#define Index_Store_Tag_D 0x09
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#define Hit_Invalidate_I 0x10
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#define Hit_Invalidate_D 0x11
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#define Hit_Writeback_Inv_D 0x15
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3\n\t \n" \
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" cache %0, %1 \n" \
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" .set pop \n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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#define CKSEG0 0x80000000
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/*
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* These definitions are correct for the 24K/34K/74K SPRAM sample
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* implementation. The 4KS interpreted the tags differently...
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*/
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#define SPRAM_TAG0_ENABLE 0x00000080
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#define SPRAM_TAG0_PA_MASK 0xfffff000
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#define SPRAM_TAG1_SIZE_MASK 0xfffff000
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#define SPRAM_TAG_STRIDE 8
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#define ERRCTL_SPRAM (1 << 28)
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/*
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* Macros to access the system control coprocessor
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*/
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#define __read_32bit_c0_register(source, sel) \
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({ int __res; \
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if (sel == 0) \
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__asm__ __volatile__( \
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"mfc0\t%0, " #source "\n\t" \
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: "=r" (__res)); \
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else \
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__asm__ __volatile__( \
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".set\tmips32\n\t" \
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"mfc0\t%0, " #source ", " #sel "\n\t" \
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".set\tmips0\n\t" \
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: "=r" (__res)); \
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__res; \
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})
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#define __write_32bit_c0_register(register, sel, value) \
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do { \
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if (sel == 0) \
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__asm__ __volatile__( \
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"mtc0\t%z0, " #register "\n\t" \
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: : "Jr" ((unsigned int)(value))); \
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else \
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__asm__ __volatile__( \
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".set\tmips32\n\t" \
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"mtc0\t%z0, " #register ", " #sel "\n\t" \
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".set\tmips0" \
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: : "Jr" ((unsigned int)(value))); \
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} while (0)
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#define read_c0_ecc() __read_32bit_c0_register($26, 0)
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#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
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#define read_c0_taglo() __read_32bit_c0_register($28, 0)
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#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
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#define read_c0_idatalo() __read_32bit_c0_register($28, 1)
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#define write_c0_idatalo(val) __write_32bit_c0_register($28, 1, val)
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#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
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#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
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#define read_c0_idatahi() __read_32bit_c0_register($29, 1)
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#define write_c0_idatahi(val) __write_32bit_c0_register($29, 1, val)
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#define read_c0_config() __read_32bit_c0_register($16, 0)
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#define PHYS_TO_K0(x) (((uint32)x) | 0x80000000)
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#define K0_TO_PHYS(x) (((uint32)x) & 0x7fffffff)
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/* errctl access */
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#define read_c0_errctl(x) read_c0_ecc(x)
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#define write_c0_errctl(x) write_c0_ecc(x)
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static inline void ehb(void)
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{
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__asm__ __volatile__(
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" .set mips32r2 \n"
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" ehb \n"
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" .set mips0 \n");
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}
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/*
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* Different semantics to the set_c0_* function built by __BUILD_SET_C0
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*/
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static unsigned int bis_c0_errctl(unsigned int set)
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{
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unsigned int res;
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res = read_c0_errctl();
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write_c0_errctl(res | set);
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return res;
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}
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static void ispram_store_data(unsigned int offset, unsigned int datalo, unsigned int datahi)
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{
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unsigned int errctl;
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/* enable SPRAM tag access */
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errctl = bis_c0_errctl(ERRCTL_SPRAM);
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ehb();
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#ifdef CONFIG_CPU_BIG_ENDIAN
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write_c0_idatalo(datahi);
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ehb();
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write_c0_idatahi(datalo);
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ehb();
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#else
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write_c0_idatalo(datalo);
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ehb();
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write_c0_idatahi(datahi);
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ehb();
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#endif
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cache_op(MIPS34K_Index_Store_Data_I, CKSEG0|offset);
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ehb();
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write_c0_errctl(errctl);
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ehb();
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}
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static void ispram_store_tag(unsigned int offset, unsigned int data)
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{
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unsigned int errctl;
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/* enable SPRAM tag access */
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errctl = bis_c0_errctl(ERRCTL_SPRAM);
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ehb();
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write_c0_taglo(data);
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ehb();
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cache_op(Index_Store_Tag_I, CKSEG0|offset);
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ehb();
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write_c0_errctl(errctl);
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ehb();
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}
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static unsigned int ispram_load_tag(unsigned int offset)
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{
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unsigned int data;
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unsigned int errctl;
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/* enable SPRAM tag access */
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errctl = bis_c0_errctl(ERRCTL_SPRAM);
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ehb();
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cache_op(Index_Load_Tag_I, CKSEG0 | offset);
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ehb();
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data = read_c0_taglo();
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ehb();
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write_c0_errctl(errctl);
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ehb();
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return data;
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}
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static void dspram_store_tag(unsigned int offset, unsigned int data)
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{
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unsigned int errctl;
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/* enable SPRAM tag access */
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errctl = bis_c0_errctl(ERRCTL_SPRAM);
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ehb();
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write_c0_dtaglo(data);
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ehb();
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cache_op(Index_Store_Tag_D, CKSEG0 | offset);
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ehb();
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write_c0_errctl(errctl);
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ehb();
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}
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static unsigned int dspram_load_tag(unsigned int offset)
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{
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unsigned int data;
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unsigned int errctl;
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errctl = bis_c0_errctl(ERRCTL_SPRAM);
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ehb();
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cache_op(Index_Load_Tag_D, CKSEG0 | offset);
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ehb();
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data = read_c0_dtaglo();
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ehb();
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write_c0_errctl(errctl);
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ehb();
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return data;
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}
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/*
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enable:
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0:disable dspram
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1:enable dspram
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2:disable ispram
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3:enable ispram
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*/
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void probe_spram(unsigned int base, unsigned int enable)
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{
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unsigned int offset = 0;
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unsigned int size, tag0, tag1;
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unsigned int enabled;
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int i;
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unsigned int type = (enable & 0x2) >> 0x1;
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if(type){
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tag0 = ispram_load_tag(offset);
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tag1 = ispram_load_tag(offset+SPRAM_TAG_STRIDE);
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}
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else{
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tag0 = dspram_load_tag(offset);
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tag1 = dspram_load_tag(offset+SPRAM_TAG_STRIDE);
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}
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size = tag1 & SPRAM_TAG1_SIZE_MASK;
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if (size == 0)
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return;
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/* Align base with size */
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base = (base + size - 1) & ~(size-1);
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/* reprogram the base address base address and enable */
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if(enable & 0x1)
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tag0 = (base & SPRAM_TAG0_PA_MASK) | SPRAM_TAG0_ENABLE;
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else
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tag0 = (base & SPRAM_TAG0_PA_MASK);
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//write(offset, tag0);
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if(type){
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ispram_store_tag(offset, tag0);
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}
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else{
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dspram_store_tag(offset, tag0);
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}
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return;
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}
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#if 0
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/*
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enable:
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0:disable dspram
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1:enable dspram
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2:disable ispram
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3:enable ispram
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*/
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void probe_spram(unsigned int base, unsigned int enable)
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{
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unsigned int firstsize = 0, lastsize = 0;
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unsigned int firstpa = 0, lastpa = 0, pa = 0;
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unsigned int offset = 0;
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unsigned int size, tag0, tag1;
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unsigned int enabled;
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int i;
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unsigned int type = (enable & 0x2) >> 0x1;
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/*
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* The limit is arbitrary but avoids the loop running away if
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* the SPRAM tags are implemented differently
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*/
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for (i = 0; i < 8; i++) {
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if(type){
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tag0 = ispram_load_tag(offset);
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tag1 = ispram_load_tag(offset+SPRAM_TAG_STRIDE);
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}
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else{
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tag0 = dspram_load_tag(offset);
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tag1 = dspram_load_tag(offset+SPRAM_TAG_STRIDE);
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}
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//pr_debug("DBG %s%d: tag0=%08x tag1=%08x\n",
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// type, i, tag0, tag1);
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size = tag1 & SPRAM_TAG1_SIZE_MASK;
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if (size == 0)
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break;
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if (i != 0) {
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/* tags may repeat... */
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if ((pa == firstpa && size == firstsize) ||
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(pa == lastpa && size == lastsize))
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break;
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}
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/* Align base with size */
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base = (base + size - 1) & ~(size-1);
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/* reprogram the base address base address and enable */
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if(enable & 0x1)
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tag0 = (base & SPRAM_TAG0_PA_MASK) | SPRAM_TAG0_ENABLE;
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else
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tag0 = (base & SPRAM_TAG0_PA_MASK);
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//write(offset, tag0);
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if(type){
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ispram_store_tag(offset, tag0);
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}
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else{
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dspram_store_tag(offset, tag0);
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}
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base += size;
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/* reread the tag */
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//tag0 = read(offset);
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if(type){
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tag0 = ispram_load_tag(offset);
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}
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else{
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tag0 = dspram_load_tag(offset);
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}
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pa = tag0 & SPRAM_TAG0_PA_MASK;
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enabled = tag0 & SPRAM_TAG0_ENABLE;
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if (i == 0) {
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firstpa = pa;
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firstsize = size;
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}
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lastpa = pa;
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lastsize = size;
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offset += 2 * SPRAM_TAG_STRIDE;
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}
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}
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#endif
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void ispram_fill(int i_size, unsigned int from, unsigned int to)
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{
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unsigned int pa, size, tag0, tag1;
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unsigned int offset;
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unsigned int datalo, datahi;
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tag0 = ispram_load_tag(0);
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tag1 = ispram_load_tag(0+SPRAM_TAG_STRIDE);
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pa = tag0 & SPRAM_TAG0_PA_MASK;
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if(i_size)
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size = i_size;
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else
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size = tag1 & SPRAM_TAG1_SIZE_MASK;
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if(from)
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pa = from;
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if (size == 0)
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return;
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for (offset = 0; offset < size; offset += 8) {
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//datalo = *(unsigned int *) (PHYS_TO_K0(pa + offset));
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//datahi = *(unsigned int *) (PHYS_TO_K0(pa + offset + 4));
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datahi = *(unsigned int *) (PHYS_TO_K0(pa + offset));
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datalo = *(unsigned int *) (PHYS_TO_K0(pa + offset + 4));
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ispram_store_data(to + offset, datalo, datahi);
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}
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}
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