480 lines
18 KiB
C
Executable File
480 lines
18 KiB
C
Executable File
#ifndef MT7510_NAND_H
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#define MT7510_NAND_H
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typedef volatile unsigned short *P_U16;
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typedef volatile unsigned int *P_U32;
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#define bool uint8
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#define true 1
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#define false 0
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#define READ_REGISTER_UINT32(reg) \
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(*(volatile unsigned int * const)(reg))
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#define WRITE_REGISTER_UINT32(reg, val) \
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(*(volatile unsigned int * const)(reg)) = (val)
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#define INREG32(x) READ_REGISTER_UINT32((unsigned int *)((void*)(x)))
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#define OUTREG32(x, y) WRITE_REGISTER_UINT32((unsigned int *)((void*)(x)), (unsigned int )(y))
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#define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y))
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#define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y))
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#define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z))
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#define DRV_Reg8(addr) INREG32(addr)
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#define DRV_WriteReg8(addr, data) OUTREG32(addr, data)
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#define DRV_SetReg8(addr, data) SETREG32(addr, data)
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#define DRV_ClrReg8(addr, data) CLRREG32(addr, data)
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#define DRV_Reg16(addr) INREG32(addr)
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#define DRV_WriteReg16(addr, data) OUTREG32(addr, data)
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#define DRV_SetReg16(addr, data) SETREG32(addr, data)
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#define DRV_ClrReg16(addr, data) CLRREG32(addr, data)
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#define DRV_Reg32(addr) INREG32(addr)
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#define DRV_WriteReg32(addr, data) OUTREG32(addr, data)
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#define DRV_SetReg32(addr, data) SETREG32(addr, data)
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#define DRV_ClrReg32(addr, data) CLRREG32(addr, data)
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#define NFI_DEFAULT_ACCESS_TIMING 0xF3FFFFFF
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#define NFI_CS_NUM 1
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#define NAND_ECC_HW 1
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#define NFI_BASE 0xBFBE0000
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#define NFIECC_BASE 0xBFBE1000
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/*******************************************************************************
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* NFI Register Definition
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*******************************************************************************/
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#define NFI_CNFG_REG16 ((volatile P_U16)(NFI_BASE+0x0000))
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#define NFI_PAGEFMT_REG16 ((volatile P_U16)(NFI_BASE+0x0004))
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#define NFI_CON_REG16 ((volatile P_U16)(NFI_BASE+0x0008))
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#define NFI_ACCCON_REG32 ((volatile P_U32)(NFI_BASE+0x000C))
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#define NFI_INTR_EN_REG16 ((volatile P_U16)(NFI_BASE+0x0010))
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#define NFI_INTR_REG16 ((volatile P_U16)(NFI_BASE+0x0014))
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#define NFI_CMD_REG16 ((volatile P_U16)(NFI_BASE+0x0020))
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#define NFI_ADDRNOB_REG16 ((volatile P_U16)(NFI_BASE+0x0030))
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#define NFI_COLADDR_REG32 ((volatile P_U32)(NFI_BASE+0x0034))
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#define NFI_ROWADDR_REG32 ((volatile P_U32)(NFI_BASE+0x0038))
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#define NFI_STRDATA_REG16 ((volatile P_U16)(NFI_BASE+0x0040))
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#define NFI_DATAW_REG32 ((volatile P_U32)(NFI_BASE+0x0050))
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#define NFI_DATAR_REG32 ((volatile P_U32)(NFI_BASE+0x0054))
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#define NFI_PIO_DIRDY_REG16 ((volatile P_U16)(NFI_BASE+0x0058))
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#define NFI_STA_REG32 ((volatile P_U32)(NFI_BASE+0x0060))
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#define NFI_FIFOSTA_REG16 ((volatile P_U16)(NFI_BASE+0x0064))
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#define NFI_LOCKSTA_REG16 ((volatile P_U16)(NFI_BASE+0x0068))
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#define NFI_ADDRCNTR_REG16 ((volatile P_U16)(NFI_BASE+0x0070))
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#define NFI_STRADDR_REG32 ((volatile P_U32)(NFI_BASE+0x0080))
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#define NFI_BYTELEN_REG16 ((volatile P_U16)(NFI_BASE+0x0084))
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#define NFI_CSEL_REG16 ((volatile P_U16)(NFI_BASE+0x0090))
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#define NFI_IOCON_REG16 ((volatile P_U16)(NFI_BASE+0x0094))
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#define NFI_FDM0L_REG32 ((volatile P_U32)(NFI_BASE+0x00A0))
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#define NFI_FDM0M_REG32 ((volatile P_U32)(NFI_BASE+0x00A4))
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#define NFI_LOCK_REG16 ((volatile P_U16)(NFI_BASE+0x0100))
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#define NFI_LOCKCON_REG32 ((volatile P_U32)(NFI_BASE+0x0104))
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#define NFI_LOCKANOB_REG16 ((volatile P_U16)(NFI_BASE+0x0108))
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#define NFI_LOCK00ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0110))
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#define NFI_LOCK00FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0114))
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#define NFI_LOCK01ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0118))
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#define NFI_LOCK01FMT_REG32 ((volatile P_U32)(NFI_BASE+0x011C))
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#define NFI_LOCK02ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0120))
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#define NFI_LOCK02FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0124))
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#define NFI_LOCK03ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0128))
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#define NFI_LOCK03FMT_REG32 ((volatile P_U32)(NFI_BASE+0x012C))
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#define NFI_LOCK04ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0130))
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#define NFI_LOCK04FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0134))
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#define NFI_LOCK05ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0138))
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#define NFI_LOCK05FMT_REG32 ((volatile P_U32)(NFI_BASE+0x013C))
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#define NFI_LOCK06ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0140))
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#define NFI_LOCK06FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0144))
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#define NFI_LOCK07ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0148))
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#define NFI_LOCK07FMT_REG32 ((volatile P_U32)(NFI_BASE+0x014C))
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#define NFI_LOCK08ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0150))
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#define NFI_LOCK08FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0154))
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#define NFI_LOCK09ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0158))
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#define NFI_LOCK09FMT_REG32 ((volatile P_U32)(NFI_BASE+0x015C))
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#define NFI_LOCK10ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0160))
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#define NFI_LOCK10FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0164))
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#define NFI_LOCK11ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0168))
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#define NFI_LOCK11FMT_REG32 ((volatile P_U32)(NFI_BASE+0x016C))
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#define NFI_LOCK12ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0170))
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#define NFI_LOCK12FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0174))
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#define NFI_LOCK13ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0178))
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#define NFI_LOCK13FMT_REG32 ((volatile P_U32)(NFI_BASE+0x017C))
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#define NFI_LOCK14ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0180))
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#define NFI_LOCK14FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0184))
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#define NFI_LOCK15ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0188))
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#define NFI_LOCK15FMT_REG32 ((volatile P_U32)(NFI_BASE+0x018C))
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#define NFI_FIFODATA0_REG32 ((volatile P_U32)(NFI_BASE+0x0190))
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#define NFI_FIFODATA1_REG32 ((volatile P_U32)(NFI_BASE+0x0194))
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#define NFI_FIFODATA2_REG32 ((volatile P_U32)(NFI_BASE+0x0198))
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#define NFI_FIFODATA3_REG32 ((volatile P_U32)(NFI_BASE+0x019C))
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#define NFI_MASTERSTA_REG16 ((volatile P_U16)(NFI_BASE+0x0210))
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/*******************************************************************************
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* NFI Register Field Definition
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*******************************************************************************/
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/* NFI_CNFG */
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#define CNFG_AHB (0x0001)
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#define CNFG_READ_EN (0x0002)
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#define CNFG_DMA_BURST_EN (0x0004)
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#define CNFG_PIO_BIG_ENDIAN (0x0008)
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#define CNFG_BYTE_RW (0x0040)
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#define CNFG_HW_ECC_EN (0x0100)
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#define CNFG_AUTO_FMT_EN (0x0200)
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#define CNFG_OP_IDLE (0x0000)
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#define CNFG_OP_READ (0x1000)
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#define CNFG_OP_SRD (0x2000)
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#define CNFG_OP_PRGM (0x3000)
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#define CNFG_OP_ERASE (0x4000)
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#define CNFG_OP_RESET (0x5000)
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#define CNFG_OP_CUST (0x6000)
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#define CNFG_OP_MODE_MASK (0x7000)
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#define CNFG_OP_MODE_SHIFT (12)
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/* NFI_PAGEFMT */
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#define PAGEFMT_512 (0x0000)
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#define PAGEFMT_2K (0x0001)
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#define PAGEFMT_4K (0x0002)
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#define PAGEFMT_PAGE_MASK (0x0003)
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#define PAGEFMT_DBYTE_EN (0x0008)
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#define PAGEFMT_SPARE_16 (0x0000)
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#define PAGEFMT_SPARE_26 (0x0001)
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#define PAGEFMT_SPARE_27 (0x0002)
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#define PAGEFMT_SPARE_28 (0x0003)
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#define PAGEFMT_SPARE_MASK (0x0030)
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#define PAGEFMT_SPARE_SHIFT (4)
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#define PAGEFMT_FDM_MASK (0x0F00)
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#define PAGEFMT_FDM_SHIFT (8)
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#define PAGEFMT_FDM_ECC_MASK (0xF000)
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#define PAGEFMT_FDM_ECC_SHIFT (12)
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/* NFI_CON */
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#define CON_FIFO_FLUSH (0x0001)
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#define CON_NFI_RST (0x0002)
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#define CON_NFI_SRD (0x0010)
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#define CON_NFI_NOB_MASK (0x0060)
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#define CON_NFI_NOB_SHIFT (5)
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#define CON_NFI_BRD (0x0100)
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#define CON_NFI_BWR (0x0200)
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#define CON_NFI_SEC_MASK (0xF000)
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#define CON_NFI_SEC_SHIFT (12)
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/* NFI_ACCCON */
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#define ACCCON_SETTING ()
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/* NFI_INTR_EN */
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#define INTR_RD_DONE_EN (0x0001)
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#define INTR_WR_DONE_EN (0x0002)
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#define INTR_RST_DONE_EN (0x0004)
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#define INTR_ERASE_DONE_EN (0x0008)
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#define INTR_BSY_RTN_EN (0x0010)
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#define INTR_ACC_LOCK_EN (0x0020)
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#define INTR_AHB_DONE_EN (0x0040)
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#define INTR_ALL_INTR_DE (0x0000)
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#define INTR_ALL_INTR_EN (0x007F)
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/* NFI_INTR */
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#define INTR_RD_DONE (0x0001)
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#define INTR_WR_DONE (0x0002)
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#define INTR_RST_DONE (0x0004)
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#define INTR_ERASE_DONE (0x0008)
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#define INTR_BSY_RTN (0x0010)
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#define INTR_ACC_LOCK (0x0020)
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#define INTR_AHB_DONE (0x0040)
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/* NFI_ADDRNOB */
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#define ADDR_COL_NOB_MASK (0x0003)
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#define ADDR_COL_NOB_SHIFT (0)
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#define ADDR_ROW_NOB_MASK (0x0030)
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#define ADDR_ROW_NOB_SHIFT (4)
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/* NFI_STA */
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#define STA_READ_EMPTY (0x00001000)
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#define STA_ACC_LOCK (0x00000010)
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#define STA_CMD_STATE (0x00000001)
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#define STA_ADDR_STATE (0x00000002)
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#define STA_DATAR_STATE (0x00000004)
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#define STA_DATAW_STATE (0x00000008)
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#define STA_NAND_FSM_MASK (0x1F000000)
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#define STA_NAND_BUSY (0x00000100)
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#define STA_NAND_BUSY_RETURN (0x00000200)
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#define STA_NFI_FSM_MASK (0x000F0000)
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#define STA_NFI_OP_MASK (0x0000000F)
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/* NFI_FIFOSTA */
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#define FIFO_RD_EMPTY (0x0040)
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#define FIFO_RD_FULL (0x0080)
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#define FIFO_WR_FULL (0x8000)
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#define FIFO_WR_EMPTY (0x4000)
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#define FIFO_RD_REMAIN(x) (0x1F&(x))
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#define FIFO_WR_REMAIN(x) ((0x1F00&(x))>>8)
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/* NFI_ADDRCNTR */
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#define ADDRCNTR_CNTR(x) ((0xF000&(x))>>12)
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#define ADDRCNTR_OFFSET(x) (0x03FF&(x))
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/* NFI_LOCK */
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#define NFI_LOCK_ON (0x0001)
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/* NFI_LOCKANOB */
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#define PROG_RADD_NOB_MASK (0x7000)
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#define PROG_RADD_NOB_SHIFT (12)
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#define PROG_CADD_NOB_MASK (0x0300)
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#define PROG_CADD_NOB_SHIFT (8)
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#define ERASE_RADD_NOB_MASK (0x0070)
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#define ERASE_RADD_NOB_SHIFT (4)
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#define ERASE_CADD_NOB_MASK (0x0007)
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#define ERASE_CADD_NOB_SHIFT (0)
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/*******************************************************************************
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* ECC Register Definition
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*******************************************************************************/
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#define ECC_ENCCON_REG16 ((volatile P_U16)(NFIECC_BASE+0x0000))
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#define ECC_ENCCNFG_REG32 ((volatile P_U32)(NFIECC_BASE+0x0004))
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#define ECC_ENCDIADDR_REG32 ((volatile P_U32)(NFIECC_BASE+0x0008))
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#define ECC_ENCIDLE_REG32 ((volatile P_U32)(NFIECC_BASE+0x000C))
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#define ECC_ENCPAR0_REG32 ((volatile P_U32)(NFIECC_BASE+0x0010))
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#define ECC_ENCPAR1_REG32 ((volatile P_U32)(NFIECC_BASE+0x0014))
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#define ECC_ENCPAR2_REG32 ((volatile P_U32)(NFIECC_BASE+0x0018))
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#define ECC_ENCPAR3_REG32 ((volatile P_U32)(NFIECC_BASE+0x001C))
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#define ECC_ENCPAR4_REG32 ((volatile P_U32)(NFIECC_BASE+0x0020))
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#define ECC_ENCSTA_REG32 ((volatile P_U32)(NFIECC_BASE+0x0024))
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#define ECC_ENCIRQEN_REG16 ((volatile P_U16)(NFIECC_BASE+0x0028))
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#define ECC_ENCIRQSTA_REG16 ((volatile P_U16)(NFIECC_BASE+0x002C))
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#define ECC_DECCON_REG16 ((volatile P_U16)(NFIECC_BASE+0x0100))
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#define ECC_DECCNFG_REG32 ((volatile P_U32)(NFIECC_BASE+0x0104))
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#define ECC_DECDIADDR_REG32 ((volatile P_U32)(NFIECC_BASE+0x0108))
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#define ECC_DECIDLE_REG16 ((volatile P_U16)(NFIECC_BASE+0x010C))
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#define ECC_DECFER_REG16 ((volatile P_U16)(NFIECC_BASE+0x0110))
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#define ECC_DECENUM0_REG32 ((volatile P_U32)(NFIECC_BASE+0x0114))
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#define ECC_DECENUM1_REG32 ((volatile P_U32)(NFIECC_BASE+0x0118))
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#define ECC_DECDONE_REG16 ((volatile P_U16)(NFIECC_BASE+0x011C))
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#define ECC_DECEL0_REG32 ((volatile P_U32)(NFIECC_BASE+0x0120))
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#define ECC_DECEL1_REG32 ((volatile P_U32)(NFIECC_BASE+0x0124))
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#define ECC_DECEL2_REG32 ((volatile P_U32)(NFIECC_BASE+0x0128))
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#define ECC_DECEL3_REG32 ((volatile P_U32)(NFIECC_BASE+0x012C))
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#define ECC_DECEL4_REG32 ((volatile P_U32)(NFIECC_BASE+0x0130))
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#define ECC_DECEL5_REG32 ((volatile P_U32)(NFIECC_BASE+0x0134))
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#define ECC_DECEL6_REG32 ((volatile P_U32)(NFIECC_BASE+0x0138))
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#define ECC_DECEL7_REG32 ((volatile P_U32)(NFIECC_BASE+0x013C))
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#define ECC_DECIRQEN_REG16 ((volatile P_U16)(NFIECC_BASE+0x0140))
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#define ECC_DECIRQSTA_REG16 ((volatile P_U16)(NFIECC_BASE+0x0144))
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#define ECC_FDMADDR_REG32 ((volatile P_U32)(NFIECC_BASE+0x0148))
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#define ECC_DECFSM_REG32 ((volatile P_U32)(NFIECC_BASE+0x014C))
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#define ECC_SYNSTA_REG32 ((volatile P_U32)(NFIECC_BASE+0x0150))
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#define ECC_DECNFIDI_REG32 ((volatile P_U32)(NFIECC_BASE+0x0154))
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#define ECC_SYN0_REG32 ((volatile P_U32)(NFIECC_BASE+0x0158))
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/*******************************************************************************
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* ECC register definition
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*******************************************************************************/
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/* ECC_ENCON */
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#define ENC_EN (0x0001)
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#define ENC_DE (0x0000)
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/* ECC_ENCCNFG */
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#define ECC_CNFG_ECC4 (0x0000)
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#define ECC_CNFG_ECC6 (0x0001)
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#define ECC_CNFG_ECC8 (0x0002)
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#define ECC_CNFG_ECC10 (0x0003)
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#define ECC_CNFG_ECC12 (0x0004)
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#define ECC_CNFG_ECC_MASK (0x00000007)
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#define ENC_CNFG_NFI (0x0010)
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#define ENC_CNFG_MODE_MASK (0x0010)
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#define ENC_CNFG_META6 (0x10300000)
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#define ENC_CNFG_META8 (0x10400000)
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#define ENC_CNFG_MSG_MASK (0x1FFF0000)
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#define ENC_CNFG_MSG_SHIFT (0x10)
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/* ECC_ENCIDLE */
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#define ENC_IDLE (0x0001)
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/* ECC_ENCSTA */
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#define STA_FSM (0x001F)
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#define STA_COUNT_PS (0xFF10)
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#define STA_COUNT_MS (0x3FFF0000)
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/* ECC_ENCIRQEN */
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#define ENC_IRQEN (0x0001)
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/* ECC_ENCIRQSTA */
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#define ENC_IRQSTA (0x0001)
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/* ECC_DECCON */
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#define DEC_EN (0x0001)
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#define DEC_DE (0x0000)
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/* ECC_ENCCNFG */
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#define DEC_CNFG_ECC4 (0x0000)
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//#define DEC_CNFG_ECC6 (0x0001)
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//#define DEC_CNFG_ECC12 (0x0002)
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#define DEC_CNFG_NFI (0x0010)
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//#define DEC_CNFG_META6 (0x10300000)
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//#define DEC_CNFG_META8 (0x10400000)
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#define DEC_CNFG_BURST_EN (0x00100)
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#define DEC_CNFG_FER (0x01000)
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#define DEC_CNFG_EL (0x02000)
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#define DEC_CNFG_CORRECT (0x03000)
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#define DEC_CNFG_TYPE_MASK (0x03000)
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#define DEC_CNFG_EMPTY_EN (0x80000000)
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#define DEC_CNFG_CODE_MASK (0x1FFF0000)
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#define DEC_CNFG_CODE_SHIFT (0x10)
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/* ECC_DECIDLE */
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#define DEC_IDLE (0x0001)
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/*
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* Standard NAND flash commands
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*/
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#define NAND_CMD_READ0 0
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#define NAND_CMD_READ1 1
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#define NAND_CMD_RNDOUT 5
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#define NAND_CMD_PAGEPROG 0x10
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#define NAND_CMD_READOOB 0x50
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#define NAND_CMD_ERASE1 0x60
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#define NAND_CMD_STATUS 0x70
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#define NAND_CMD_STATUS_MULTI 0x71
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#define NAND_CMD_SEQIN 0x80
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#define NAND_CMD_RNDIN 0x85
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#define NAND_CMD_READID 0x90
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#define NAND_CMD_ERASE2 0xd0
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#define NAND_CMD_RESET 0xff
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/* Extended commands for large page devices */
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#define NAND_CMD_READSTART 0x30
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#define NAND_CMD_RNDOUTSTART 0xE0
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#define NAND_CMD_CACHEDPROG 0x15
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/* Status bits */
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#define NAND_STATUS_FAIL 0x01
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#define NAND_STATUS_FAIL_N1 0x02
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#define NAND_STATUS_TRUE_READY 0x20
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#define NAND_STATUS_READY 0x40
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#define NAND_STATUS_WP 0x80
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#define KB_SHIFT 10
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#define MB_SHIFT 20
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#define K0_TO_K1(x) (((uint32)x) | 0xa0000000)
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#define K1_TO_PHY(x) (((uint32)x) & 0x1fffffff)
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typedef struct
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{
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unsigned short id; //deviceid+menuid
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unsigned int ext_id;
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unsigned char addr_cycle;
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unsigned char iowidth;
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unsigned short totalsize;
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unsigned short blocksize;
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unsigned short pagesize;
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unsigned int timmingsetting;
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char devciename[14];
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unsigned int advancedmode; //
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}flashdev_info,*pflashdev_info;
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/* NAND driver */
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struct mt6573_nand_host_hw {
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unsigned int nfi_bus_width; /* NFI_BUS_WIDTH */
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unsigned int nfi_access_timing; /* NFI_ACCESS_TIMING */
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unsigned int nfi_cs_num; /* NFI_CS_NUM */
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unsigned int nand_sec_size; /* NAND_SECTOR_SIZE */
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unsigned int nand_sec_shift; /* NAND_SECTOR_SHIFT */
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unsigned int nand_ecc_size;
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unsigned int nand_ecc_bytes;
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unsigned int nand_ecc_mode;
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};
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struct nand_info {
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int mfr_id;
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int dev_id;
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char *name;
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int numchips;
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int chip_shift;
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int page_shift;
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int erase_shift;
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int oob_shift;
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int badblockpos;
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int opcode_type;
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};
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struct ra_nand_chip {
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|
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struct nand_info *flash;
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};
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static const flashdev_info gen_FlashTable[]={
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//st
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{0x2075, 0x207520 ,4, 8, 32, 16, 512, 0x44333, "NAND256W3A", 0}, //32M,512 Page size
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//micro
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{0x2CDA, 0x909504, 5, 8, 256, 128, 2048, 0x44333, "MT29F2G08AAB", 0}, //256M, 2K Page Size
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//{0x2CDC, 0x909504, 5, 8, 512, 128, 2048, 0x44333, "MT29F4G08AAC", 0}, //512M, 2K Page Size
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/*new add*/
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{0xC8DA, 0x909544, 5, 8, 256, 128, 2048, 0x44333, "F59L2G81A", 0},
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{0x2CDA, 0x909506, 5, 8, 256, 128, 2048, 0x44333, "MT29F2G08ABAEA", 0}, //256M, 2K Page Size
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//samsung
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{0xECDC, 0x109554, 5, 8, 512, 128, 2048, 0x44333, "K9F4G08U0D", 0},//512M, 2K Page Size
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|
//toshiba
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{0x98D1, 0x901576, 4, 8, 128, 128, 2048, 0x44333, "TC58NVG0S3E", 0}, //128M
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{0x98D3, 0x902676, 5, 8, 1024, 256, 4096, 0x44333, "TC58NVG3S0F", 0}, //1024M
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|
/*new add */
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{0x98F1, 0x8015F2, 4, 8, 128, 128, 2048, 0x44333, "TC58BVG0S3HTA00-1G", 0}, //128M
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{0x98F1, 0x801572, 4, 8, 128, 128, 2048, 0x44333, "TC58NVG0S3HTA00", 0}, //128M
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{0x98DA, 0x9015F6, 5, 8, 256, 128, 2048, 0x44333, "TC58BVG1S3HTA00-2G", 0}, //256M
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{0x98D3, 0x912676, 5, 8, 1024, 256, 4096, 0x44333, "TH58NVG3S0HTA00", 0}, //1024M,4K page
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{0x98D3, 0x9126F6, 5, 8, 1024, 256, 4096, 0x44333, "TH58BVG3S0HTA00", 0}, //1024M,4K page
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|
|
//Winbond
|
|
{0xeff1, 0x809500, 4, 8, 128, 128, 2048, 0x44333, "W29N01GV", 0}, //128M
|
|
/*new add */
|
|
{0xEFF1, 0x009500, 4, 8, 128, 128, 2048, 0x44333, "W29N01HVSINA", 0}, //128M
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|
{0xEFDA, 0x909504, 5, 8, 256, 128, 2048, 0x44333, "W29N02GVSIAA", 0}, //256M
|
|
//MXIC
|
|
{0xc2f1, 0x801dc2, 4, 8, 128, 128, 2048, 0x44333, "MX30LF1G08", 0}, //128M
|
|
{0xc2f1, 0x809502, 4, 8, 128, 128, 2048, 0x44333, "MX30LF1G18AC", 0}, //128M
|
|
/*new add */
|
|
{0xC2DA, 0x909506, 5, 8, 256, 128, 2048, 0x44333, "MX30LF2G18AC", 0}, //256M
|
|
//ESMT
|
|
{0x92f1, 0x809540, 4, 8, 128, 128, 2048, 0x44333, "F59L1G81A", 0}, //128M
|
|
/*new add */
|
|
{0xC8D1, 0x809542, 4, 8, 128, 128, 2048, 0x44333, "F59L1G81LA", 0}, //128M
|
|
{0xC8D1, 0x809540, 4, 8, 128, 128, 2048, 0x44333, "F59L1G81MA", 0}, //128M
|
|
{0x0000, 0, 0, 0, 0, 0, 0, 0, "xxxxxxxxxxxxx", 0},
|
|
};
|
|
|
|
#endif
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