528 lines
14 KiB
C
Executable File
528 lines
14 KiB
C
Executable File
/*
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* omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
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*
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* Copyright (C) 2009 - 2011 Texas Instruments
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*
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* Author: Misael Lopez Cruz <misael.lopez@ti.com>
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* Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
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* Margarita Olaya <magi.olaya@ti.com>
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* Peter Ujfalusi <peter.ujfalusi@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/of_device.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/omap-pcm.h>
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#include "omap-mcpdm.h"
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struct mcpdm_link_config {
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u32 link_mask; /* channel mask for the direction */
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u32 threshold; /* FIFO threshold */
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};
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struct omap_mcpdm {
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struct device *dev;
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unsigned long phys_base;
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void __iomem *io_base;
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int irq;
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struct mutex mutex;
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/* Playback/Capture configuration */
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struct mcpdm_link_config config[2];
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/* McPDM dn offsets for rx1, and 2 channels */
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u32 dn_rx_offset;
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/* McPDM needs to be restarted due to runtime reconfiguration */
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bool restart;
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struct snd_dmaengine_dai_dma_data dma_data[2];
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};
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/*
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* Stream DMA parameters
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*/
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static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
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{
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writel_relaxed(val, mcpdm->io_base + reg);
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}
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static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
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{
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return readl_relaxed(mcpdm->io_base + reg);
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}
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#ifdef DEBUG
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static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
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{
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dev_dbg(mcpdm->dev, "***********************\n");
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dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
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omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
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dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
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omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
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dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
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omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
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dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
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omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
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dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
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omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
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dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
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omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
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dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
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omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
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dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
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omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
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dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
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omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
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dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
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omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
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dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
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omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
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dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
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omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
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dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
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omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
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dev_dbg(mcpdm->dev, "***********************\n");
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}
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#else
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static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
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#endif
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/*
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* Enables the transfer through the PDM interface to/from the Phoenix
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* codec by enabling the corresponding UP or DN channels.
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*/
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static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
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{
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u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
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u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;
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ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
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ctrl |= link_mask;
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
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ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
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}
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/*
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* Disables the transfer through the PDM interface to/from the Phoenix
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* codec by disabling the corresponding UP or DN channels.
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*/
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static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
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{
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u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
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u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK;
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ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
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ctrl &= ~(link_mask);
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
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ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
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}
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/*
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* Is the physical McPDM interface active.
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*/
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static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
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{
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return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
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(MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
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}
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/*
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* Configures McPDM uplink, and downlink for audio.
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* This function should be called before omap_mcpdm_start.
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*/
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static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
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{
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omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
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MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
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MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
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/* Enable DN RX1/2 offset cancellation feature, if configured */
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if (mcpdm->dn_rx_offset) {
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u32 dn_offset = mcpdm->dn_rx_offset;
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omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
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dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
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omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
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}
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omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
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mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
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omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
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mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
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omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
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MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
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}
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/*
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* Cleans McPDM uplink, and downlink configuration.
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* This function should be called when the stream is closed.
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*/
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static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
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{
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/* Disable irq request generation for downlink */
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omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
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MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
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/* Disable DMA request generation for downlink */
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omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
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/* Disable irq request generation for uplink */
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omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
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MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
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/* Disable DMA request generation for uplink */
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omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
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/* Disable RX1/2 offset cancellation */
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if (mcpdm->dn_rx_offset)
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omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
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}
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static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
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{
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struct omap_mcpdm *mcpdm = dev_id;
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int irq_status;
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irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
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/* Acknowledge irq event */
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omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
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if (irq_status & MCPDM_DN_IRQ_FULL)
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dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
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if (irq_status & MCPDM_DN_IRQ_EMPTY)
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dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
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if (irq_status & MCPDM_DN_IRQ)
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dev_dbg(mcpdm->dev, "DN (playback) write request\n");
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if (irq_status & MCPDM_UP_IRQ_FULL)
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dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
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if (irq_status & MCPDM_UP_IRQ_EMPTY)
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dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
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if (irq_status & MCPDM_UP_IRQ)
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dev_dbg(mcpdm->dev, "UP (capture) write request\n");
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return IRQ_HANDLED;
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}
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static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
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mutex_lock(&mcpdm->mutex);
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if (!dai->active) {
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u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
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omap_mcpdm_open_streams(mcpdm);
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}
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mutex_unlock(&mcpdm->mutex);
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return 0;
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}
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static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
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mutex_lock(&mcpdm->mutex);
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if (!dai->active) {
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if (omap_mcpdm_active(mcpdm)) {
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omap_mcpdm_stop(mcpdm);
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omap_mcpdm_close_streams(mcpdm);
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mcpdm->config[0].link_mask = 0;
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mcpdm->config[1].link_mask = 0;
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}
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}
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mutex_unlock(&mcpdm->mutex);
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}
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static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
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int stream = substream->stream;
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struct snd_dmaengine_dai_dma_data *dma_data;
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u32 threshold;
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int channels;
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int link_mask = 0;
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channels = params_channels(params);
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switch (channels) {
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case 5:
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if (stream == SNDRV_PCM_STREAM_CAPTURE)
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/* up to 3 channels for capture */
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return -EINVAL;
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link_mask |= 1 << 4;
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case 4:
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if (stream == SNDRV_PCM_STREAM_CAPTURE)
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/* up to 3 channels for capture */
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return -EINVAL;
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link_mask |= 1 << 3;
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case 3:
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link_mask |= 1 << 2;
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case 2:
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link_mask |= 1 << 1;
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case 1:
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link_mask |= 1 << 0;
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break;
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default:
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/* unsupported number of channels */
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return -EINVAL;
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}
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dma_data = snd_soc_dai_get_dma_data(dai, substream);
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threshold = mcpdm->config[stream].threshold;
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/* Configure McPDM channels, and DMA packet size */
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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link_mask <<= 3;
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/* If capture is not running assume a stereo stream to come */
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if (!mcpdm->config[!stream].link_mask)
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mcpdm->config[!stream].link_mask = 0x3;
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dma_data->maxburst =
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(MCPDM_DN_THRES_MAX - threshold) * channels;
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} else {
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/* If playback is not running assume a stereo stream to come */
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if (!mcpdm->config[!stream].link_mask)
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mcpdm->config[!stream].link_mask = (0x3 << 3);
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dma_data->maxburst = threshold * channels;
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}
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/* Check if we need to restart McPDM with this stream */
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if (mcpdm->config[stream].link_mask &&
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mcpdm->config[stream].link_mask != link_mask)
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mcpdm->restart = true;
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mcpdm->config[stream].link_mask = link_mask;
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return 0;
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}
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static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
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if (!omap_mcpdm_active(mcpdm)) {
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omap_mcpdm_start(mcpdm);
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omap_mcpdm_reg_dump(mcpdm);
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} else if (mcpdm->restart) {
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omap_mcpdm_stop(mcpdm);
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omap_mcpdm_start(mcpdm);
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mcpdm->restart = false;
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omap_mcpdm_reg_dump(mcpdm);
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}
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return 0;
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}
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static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
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.startup = omap_mcpdm_dai_startup,
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.shutdown = omap_mcpdm_dai_shutdown,
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.hw_params = omap_mcpdm_dai_hw_params,
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.prepare = omap_mcpdm_prepare,
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};
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static int omap_mcpdm_probe(struct snd_soc_dai *dai)
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{
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struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
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int ret;
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pm_runtime_enable(mcpdm->dev);
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/* Disable lines while request is ongoing */
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pm_runtime_get_sync(mcpdm->dev);
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omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
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ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler,
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0, "McPDM", (void *)mcpdm);
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pm_runtime_put_sync(mcpdm->dev);
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if (ret) {
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dev_err(mcpdm->dev, "Request for IRQ failed\n");
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pm_runtime_disable(mcpdm->dev);
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}
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/* Configure McPDM threshold values */
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mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
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mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
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MCPDM_UP_THRES_MAX - 3;
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snd_soc_dai_init_dma_data(dai,
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&mcpdm->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
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&mcpdm->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
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return ret;
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}
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static int omap_mcpdm_remove(struct snd_soc_dai *dai)
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{
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struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
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pm_runtime_disable(mcpdm->dev);
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return 0;
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}
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#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
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#define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
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static struct snd_soc_dai_driver omap_mcpdm_dai = {
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.probe = omap_mcpdm_probe,
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.remove = omap_mcpdm_remove,
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.probe_order = SND_SOC_COMP_ORDER_LATE,
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.remove_order = SND_SOC_COMP_ORDER_EARLY,
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.playback = {
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.channels_min = 1,
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.channels_max = 5,
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.rates = OMAP_MCPDM_RATES,
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.formats = OMAP_MCPDM_FORMATS,
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.sig_bits = 24,
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},
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.capture = {
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.channels_min = 1,
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.channels_max = 3,
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.rates = OMAP_MCPDM_RATES,
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.formats = OMAP_MCPDM_FORMATS,
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.sig_bits = 24,
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},
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.ops = &omap_mcpdm_dai_ops,
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};
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static const struct snd_soc_component_driver omap_mcpdm_component = {
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.name = "omap-mcpdm",
|
|
};
|
|
|
|
void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
|
|
u8 rx1, u8 rx2)
|
|
{
|
|
struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
|
|
|
|
mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
|
|
|
|
static int asoc_mcpdm_probe(struct platform_device *pdev)
|
|
{
|
|
struct omap_mcpdm *mcpdm;
|
|
struct resource *res;
|
|
int ret;
|
|
|
|
mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
|
|
if (!mcpdm)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, mcpdm);
|
|
|
|
mutex_init(&mcpdm->mutex);
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
|
|
if (res == NULL)
|
|
return -ENOMEM;
|
|
|
|
mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
|
|
mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;
|
|
|
|
mcpdm->dma_data[0].filter_data = "dn_link";
|
|
mcpdm->dma_data[1].filter_data = "up_link";
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
|
|
mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(mcpdm->io_base))
|
|
return PTR_ERR(mcpdm->io_base);
|
|
|
|
mcpdm->irq = platform_get_irq(pdev, 0);
|
|
if (mcpdm->irq < 0)
|
|
return mcpdm->irq;
|
|
|
|
mcpdm->dev = &pdev->dev;
|
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev,
|
|
&omap_mcpdm_component,
|
|
&omap_mcpdm_dai, 1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return omap_pcm_platform_register(&pdev->dev);
|
|
}
|
|
|
|
static const struct of_device_id omap_mcpdm_of_match[] = {
|
|
{ .compatible = "ti,omap4-mcpdm", },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
|
|
|
|
static struct platform_driver asoc_mcpdm_driver = {
|
|
.driver = {
|
|
.name = "omap-mcpdm",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = omap_mcpdm_of_match,
|
|
},
|
|
|
|
.probe = asoc_mcpdm_probe,
|
|
};
|
|
|
|
module_platform_driver(asoc_mcpdm_driver);
|
|
|
|
MODULE_ALIAS("platform:omap-mcpdm");
|
|
MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
|
|
MODULE_DESCRIPTION("OMAP PDM SoC Interface");
|
|
MODULE_LICENSE("GPL");
|