361 lines
10 KiB
C
Executable File
361 lines
10 KiB
C
Executable File
/* $Revision: 3.0 $$Date: 1998/11/02 14:20:59 $
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* linux/include/linux/cyclades.h
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*
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* This file was initially written by
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* Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by
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* Ivan Passos <ivan@cyclades.com>.
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*
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* This file contains the general definitions for the cyclades.c driver
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*$Log: cyclades.h,v $
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*Revision 3.1 2002/01/29 11:36:16 henrique
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*added throttle field on struct cyclades_port to indicate whether the
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*port is throttled or not
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*
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*Revision 3.1 2000/04/19 18:52:52 ivan
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*converted address fields to unsigned long and added fields for physical
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*addresses on cyclades_card structure;
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*
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*Revision 3.0 1998/11/02 14:20:59 ivan
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*added nports field on cyclades_card structure;
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*
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*Revision 2.5 1998/08/03 16:57:01 ivan
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*added cyclades_idle_stats structure;
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*
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*Revision 2.4 1998/06/01 12:09:53 ivan
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*removed closing_wait2 from cyclades_port structure;
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*
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*Revision 2.3 1998/03/16 18:01:12 ivan
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*changes in the cyclades_port structure to get it closer to the
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*standard serial port structure;
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*added constants for new ioctls;
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*
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*Revision 2.2 1998/02/17 16:50:00 ivan
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*changes in the cyclades_port structure (addition of shutdown_wait and
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*chip_rev variables);
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*added constants for new ioctls and for CD1400 rev. numbers.
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*
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*Revision 2.1 1997/10/24 16:03:00 ivan
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*added rflow (which allows enabling the CD1400 special flow control
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*feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to
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*cyclades_port structure;
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*added Alpha support
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*
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*Revision 2.0 1997/06/30 10:30:00 ivan
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*added some new doorbell command constants related to IOCTLW and
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*UART error signaling
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*
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*Revision 1.8 1997/06/03 15:30:00 ivan
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*added constant ZFIRM_HLT
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*added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin)
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*
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*Revision 1.7 1997/03/26 10:30:00 daniel
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*new entries at the end of cyclades_port struct to reallocate
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*variables illegally allocated within card memory.
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*
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*Revision 1.6 1996/09/09 18:35:30 bentson
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*fold in changes for Cyclom-Z -- including structures for
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*communicating with board as well modest changes to original
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*structures to support new features.
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*
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*Revision 1.5 1995/11/13 21:13:31 bentson
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*changes suggested by Michael Chastain <mec@duracef.shout.net>
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*to support use of this file in non-kernel applications
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*
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*
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*/
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#ifndef _LINUX_CYCLADES_H
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#define _LINUX_CYCLADES_H
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#include <uapi/linux/cyclades.h>
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/* Per card data structure */
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struct cyclades_card {
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void __iomem *base_addr;
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union {
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void __iomem *p9050;
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struct RUNTIME_9060 __iomem *p9060;
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} ctl_addr;
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struct BOARD_CTRL __iomem *board_ctrl; /* cyz specific */
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int irq;
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unsigned int num_chips; /* 0 if card absent, -1 if Z/PCI, else Y */
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unsigned int first_line; /* minor number of first channel on card */
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unsigned int nports; /* Number of ports in the card */
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int bus_index; /* address shift - 0 for ISA, 1 for PCI */
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int intr_enabled; /* FW Interrupt flag - 0 disabled, 1 enabled */
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u32 hw_ver;
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spinlock_t card_lock;
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struct cyclades_port *ports;
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};
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/***************************************
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* Memory access functions/macros *
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* (required to support Alpha systems) *
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***************************************/
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#define cy_writeb(port,val) do { writeb((val), (port)); mb(); } while (0)
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#define cy_writew(port,val) do { writew((val), (port)); mb(); } while (0)
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#define cy_writel(port,val) do { writel((val), (port)); mb(); } while (0)
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/*
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* Statistics counters
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*/
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struct cyclades_icount {
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__u32 cts, dsr, rng, dcd, tx, rx;
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__u32 frame, parity, overrun, brk;
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__u32 buf_overrun;
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};
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/*
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* This is our internal structure for each serial port's state.
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*
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* Many fields are paralleled by the structure used by the serial_struct
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* structure.
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*
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* For definitions of the flags field, see tty.h
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*/
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struct cyclades_port {
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int magic;
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struct tty_port port;
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struct cyclades_card *card;
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union {
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struct {
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void __iomem *base_addr;
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} cyy;
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struct {
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struct CH_CTRL __iomem *ch_ctrl;
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struct BUF_CTRL __iomem *buf_ctrl;
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} cyz;
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} u;
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int line;
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int flags; /* defined in tty.h */
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int type; /* UART type */
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int read_status_mask;
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int ignore_status_mask;
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int timeout;
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int xmit_fifo_size;
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int cor1,cor2,cor3,cor4,cor5;
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int tbpr,tco,rbpr,rco;
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int baud;
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int rflow;
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int rtsdtr_inv;
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int chip_rev;
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int custom_divisor;
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u8 x_char; /* to be pushed out ASAP */
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int breakon;
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int breakoff;
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int xmit_head;
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int xmit_tail;
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int xmit_cnt;
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int default_threshold;
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int default_timeout;
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unsigned long rflush_count;
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struct cyclades_monitor mon;
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struct cyclades_idle_stats idle_stats;
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struct cyclades_icount icount;
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struct completion shutdown_wait;
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int throttle;
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};
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#define CLOSING_WAIT_DELAY 30*HZ
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#define CY_CLOSING_WAIT_NONE ASYNC_CLOSING_WAIT_NONE
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#define CY_CLOSING_WAIT_INF ASYNC_CLOSING_WAIT_INF
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#define CyMAX_CHIPS_PER_CARD 8
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#define CyMAX_CHAR_FIFO 12
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#define CyPORTS_PER_CHIP 4
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#define CD1400_MAX_SPEED 115200
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#define CyISA_Ywin 0x2000
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#define CyPCI_Ywin 0x4000
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#define CyPCI_Yctl 0x80
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#define CyPCI_Zctl CTRL_WINDOW_SIZE
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#define CyPCI_Zwin 0x80000
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#define CyPCI_Ze_win (2 * CyPCI_Zwin)
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#define PCI_DEVICE_ID_MASK 0x06
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/**** CD1400 registers ****/
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#define CD1400_REV_G 0x46
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#define CD1400_REV_J 0x48
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#define CyRegSize 0x0400
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#define Cy_HwReset 0x1400
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#define Cy_ClrIntr 0x1800
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#define Cy_EpldRev 0x1e00
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/* Global Registers */
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#define CyGFRCR (0x40*2)
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#define CyRevE (44)
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#define CyCAR (0x68*2)
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#define CyCHAN_0 (0x00)
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#define CyCHAN_1 (0x01)
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#define CyCHAN_2 (0x02)
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#define CyCHAN_3 (0x03)
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#define CyGCR (0x4B*2)
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#define CyCH0_SERIAL (0x00)
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#define CyCH0_PARALLEL (0x80)
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#define CySVRR (0x67*2)
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#define CySRModem (0x04)
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#define CySRTransmit (0x02)
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#define CySRReceive (0x01)
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#define CyRICR (0x44*2)
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#define CyTICR (0x45*2)
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#define CyMICR (0x46*2)
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#define CyICR0 (0x00)
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#define CyICR1 (0x01)
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#define CyICR2 (0x02)
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#define CyICR3 (0x03)
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#define CyRIR (0x6B*2)
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#define CyTIR (0x6A*2)
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#define CyMIR (0x69*2)
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#define CyIRDirEq (0x80)
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#define CyIRBusy (0x40)
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#define CyIRUnfair (0x20)
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#define CyIRContext (0x1C)
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#define CyIRChannel (0x03)
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#define CyPPR (0x7E*2)
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#define CyCLOCK_20_1MS (0x27)
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#define CyCLOCK_25_1MS (0x31)
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#define CyCLOCK_25_5MS (0xf4)
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#define CyCLOCK_60_1MS (0x75)
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#define CyCLOCK_60_2MS (0xea)
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/* Virtual Registers */
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#define CyRIVR (0x43*2)
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#define CyTIVR (0x42*2)
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#define CyMIVR (0x41*2)
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#define CyIVRMask (0x07)
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#define CyIVRRxEx (0x07)
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#define CyIVRRxOK (0x03)
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#define CyIVRTxOK (0x02)
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#define CyIVRMdmOK (0x01)
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#define CyTDR (0x63*2)
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#define CyRDSR (0x62*2)
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#define CyTIMEOUT (0x80)
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#define CySPECHAR (0x70)
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#define CyBREAK (0x08)
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#define CyPARITY (0x04)
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#define CyFRAME (0x02)
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#define CyOVERRUN (0x01)
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#define CyMISR (0x4C*2)
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/* see CyMCOR_ and CyMSVR_ for bits*/
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#define CyEOSRR (0x60*2)
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/* Channel Registers */
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#define CyLIVR (0x18*2)
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#define CyMscsr (0x01)
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#define CyTdsr (0x02)
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#define CyRgdsr (0x03)
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#define CyRedsr (0x07)
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#define CyCCR (0x05*2)
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/* Format 1 */
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#define CyCHAN_RESET (0x80)
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#define CyCHIP_RESET (0x81)
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#define CyFlushTransFIFO (0x82)
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/* Format 2 */
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#define CyCOR_CHANGE (0x40)
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#define CyCOR1ch (0x02)
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#define CyCOR2ch (0x04)
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#define CyCOR3ch (0x08)
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/* Format 3 */
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#define CySEND_SPEC_1 (0x21)
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#define CySEND_SPEC_2 (0x22)
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#define CySEND_SPEC_3 (0x23)
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#define CySEND_SPEC_4 (0x24)
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/* Format 4 */
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#define CyCHAN_CTL (0x10)
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#define CyDIS_RCVR (0x01)
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#define CyENB_RCVR (0x02)
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#define CyDIS_XMTR (0x04)
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#define CyENB_XMTR (0x08)
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#define CySRER (0x06*2)
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#define CyMdmCh (0x80)
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#define CyRxData (0x10)
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#define CyTxRdy (0x04)
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#define CyTxMpty (0x02)
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#define CyNNDT (0x01)
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#define CyCOR1 (0x08*2)
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#define CyPARITY_NONE (0x00)
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#define CyPARITY_0 (0x20)
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#define CyPARITY_1 (0xA0)
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#define CyPARITY_E (0x40)
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#define CyPARITY_O (0xC0)
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#define Cy_1_STOP (0x00)
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#define Cy_1_5_STOP (0x04)
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#define Cy_2_STOP (0x08)
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#define Cy_5_BITS (0x00)
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#define Cy_6_BITS (0x01)
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#define Cy_7_BITS (0x02)
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#define Cy_8_BITS (0x03)
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#define CyCOR2 (0x09*2)
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#define CyIXM (0x80)
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#define CyTxIBE (0x40)
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#define CyETC (0x20)
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#define CyAUTO_TXFL (0x60)
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#define CyLLM (0x10)
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#define CyRLM (0x08)
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#define CyRtsAO (0x04)
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#define CyCtsAE (0x02)
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#define CyDsrAE (0x01)
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#define CyCOR3 (0x0A*2)
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#define CySPL_CH_DRANGE (0x80) /* special character detect range */
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#define CySPL_CH_DET1 (0x40) /* enable special character detection
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on SCHR4-SCHR3 */
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#define CyFL_CTRL_TRNSP (0x20) /* Flow Control Transparency */
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#define CySPL_CH_DET2 (0x10) /* Enable special character detection
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on SCHR2-SCHR1 */
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#define CyREC_FIFO (0x0F) /* Receive FIFO threshold */
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#define CyCOR4 (0x1E*2)
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#define CyCOR5 (0x1F*2)
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#define CyCCSR (0x0B*2)
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#define CyRxEN (0x80)
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#define CyRxFloff (0x40)
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#define CyRxFlon (0x20)
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#define CyTxEN (0x08)
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#define CyTxFloff (0x04)
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#define CyTxFlon (0x02)
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#define CyRDCR (0x0E*2)
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#define CySCHR1 (0x1A*2)
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#define CySCHR2 (0x1B*2)
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#define CySCHR3 (0x1C*2)
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#define CySCHR4 (0x1D*2)
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#define CySCRL (0x22*2)
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#define CySCRH (0x23*2)
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#define CyLNC (0x24*2)
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#define CyMCOR1 (0x15*2)
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#define CyMCOR2 (0x16*2)
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#define CyRTPR (0x21*2)
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#define CyMSVR1 (0x6C*2)
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#define CyMSVR2 (0x6D*2)
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#define CyANY_DELTA (0xF0)
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#define CyDSR (0x80)
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#define CyCTS (0x40)
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#define CyRI (0x20)
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#define CyDCD (0x10)
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#define CyDTR (0x02)
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#define CyRTS (0x01)
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#define CyPVSR (0x6F*2)
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#define CyRBPR (0x78*2)
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#define CyRCOR (0x7C*2)
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#define CyTBPR (0x72*2)
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#define CyTCOR (0x76*2)
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/* Custom Registers */
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#define CyPLX_VER (0x3400)
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#define PLX_9050 0x0b
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#define PLX_9060 0x0c
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#define PLX_9080 0x0d
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/***************************************************************************/
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#endif /* _LINUX_CYCLADES_H */
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