798 lines
20 KiB
C
Executable File
798 lines
20 KiB
C
Executable File
/*
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* drivers/pcmcia/m32r_cfc.c
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*
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* Device driver for the CFC functionality of M32R.
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*
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* Copyright (c) 2001, 2002, 2003, 2004
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* Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/fcntl.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/timer.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/workqueue.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/bitops.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <pcmcia/ss.h>
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#undef MAX_IO_WIN /* FIXME */
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#define MAX_IO_WIN 1
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#undef MAX_WIN /* FIXME */
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#define MAX_WIN 1
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#include "m32r_cfc.h"
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/* Poll status interval -- 0 means default to interrupt */
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static int poll_interval = 0;
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typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
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typedef struct pcc_socket {
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u_short type, flags;
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struct pcmcia_socket socket;
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unsigned int number;
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unsigned int ioaddr;
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u_long mapaddr;
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u_long base; /* PCC register base */
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u_char cs_irq1, cs_irq2, intr;
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pccard_io_map io_map[MAX_IO_WIN];
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pccard_mem_map mem_map[MAX_WIN];
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u_char io_win;
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u_char mem_win;
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pcc_as_t current_space;
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u_char last_iodbex;
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#ifdef CONFIG_PROC_FS
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struct proc_dir_entry *proc;
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#endif
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} pcc_socket_t;
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static int pcc_sockets = 0;
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static pcc_socket_t socket[M32R_MAX_PCC] = {
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{ 0, }, /* ... */
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};
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/*====================================================================*/
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static unsigned int pcc_get(u_short, unsigned int);
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static void pcc_set(u_short, unsigned int , unsigned int );
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static DEFINE_SPINLOCK(pcc_lock);
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#if !defined(CONFIG_PLAT_USRV)
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static inline u_long pcc_port2addr(unsigned long port, int size) {
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u_long addr = 0;
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u_long odd;
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if (size == 1) { /* byte access */
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odd = (port&1) << 11;
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port -= port & 1;
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addr = CFC_IO_MAPBASE_BYTE - CFC_IOPORT_BASE + odd + port;
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} else if (size == 2)
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addr = CFC_IO_MAPBASE_WORD - CFC_IOPORT_BASE + port;
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return addr;
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}
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#else /* CONFIG_PLAT_USRV */
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static inline u_long pcc_port2addr(unsigned long port, int size) {
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u_long odd;
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u_long addr = ((port - CFC_IOPORT_BASE) & 0xf000) << 8;
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if (size == 1) { /* byte access */
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odd = port & 1;
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port -= odd;
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odd <<= 11;
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addr = (addr | CFC_IO_MAPBASE_BYTE) + odd + (port & 0xfff);
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} else if (size == 2) /* word access */
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addr = (addr | CFC_IO_MAPBASE_WORD) + (port & 0xfff);
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return addr;
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}
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#endif /* CONFIG_PLAT_USRV */
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void pcc_ioread_byte(int sock, unsigned long port, void *buf, size_t size,
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size_t nmemb, int flag)
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{
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u_long addr;
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unsigned char *bp = (unsigned char *)buf;
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unsigned long flags;
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pr_debug("m32r_cfc: pcc_ioread_byte: sock=%d, port=%#lx, buf=%p, "
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"size=%u, nmemb=%d, flag=%d\n",
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sock, port, buf, size, nmemb, flag);
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addr = pcc_port2addr(port, 1);
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if (!addr) {
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printk("m32r_cfc:ioread_byte null port :%#lx\n",port);
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return;
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}
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pr_debug("m32r_cfc: pcc_ioread_byte: addr=%#lx\n", addr);
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spin_lock_irqsave(&pcc_lock, flags);
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/* read Byte */
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while (nmemb--)
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*bp++ = readb(addr);
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spin_unlock_irqrestore(&pcc_lock, flags);
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}
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void pcc_ioread_word(int sock, unsigned long port, void *buf, size_t size,
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size_t nmemb, int flag)
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{
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u_long addr;
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unsigned short *bp = (unsigned short *)buf;
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unsigned long flags;
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pr_debug("m32r_cfc: pcc_ioread_word: sock=%d, port=%#lx, "
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"buf=%p, size=%u, nmemb=%d, flag=%d\n",
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sock, port, buf, size, nmemb, flag);
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if (size != 2)
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printk("m32r_cfc: ioread_word :illigal size %u : %#lx\n", size,
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port);
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if (size == 9)
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printk("m32r_cfc: ioread_word :insw \n");
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addr = pcc_port2addr(port, 2);
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if (!addr) {
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printk("m32r_cfc:ioread_word null port :%#lx\n",port);
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return;
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}
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pr_debug("m32r_cfc: pcc_ioread_word: addr=%#lx\n", addr);
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spin_lock_irqsave(&pcc_lock, flags);
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/* read Word */
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while (nmemb--)
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*bp++ = readw(addr);
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spin_unlock_irqrestore(&pcc_lock, flags);
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}
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void pcc_iowrite_byte(int sock, unsigned long port, void *buf, size_t size,
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size_t nmemb, int flag)
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{
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u_long addr;
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unsigned char *bp = (unsigned char *)buf;
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unsigned long flags;
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pr_debug("m32r_cfc: pcc_iowrite_byte: sock=%d, port=%#lx, "
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"buf=%p, size=%u, nmemb=%d, flag=%d\n",
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sock, port, buf, size, nmemb, flag);
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/* write Byte */
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addr = pcc_port2addr(port, 1);
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if (!addr) {
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printk("m32r_cfc:iowrite_byte null port:%#lx\n",port);
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return;
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}
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pr_debug("m32r_cfc: pcc_iowrite_byte: addr=%#lx\n", addr);
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spin_lock_irqsave(&pcc_lock, flags);
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while (nmemb--)
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writeb(*bp++, addr);
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spin_unlock_irqrestore(&pcc_lock, flags);
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}
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void pcc_iowrite_word(int sock, unsigned long port, void *buf, size_t size,
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size_t nmemb, int flag)
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{
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u_long addr;
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unsigned short *bp = (unsigned short *)buf;
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unsigned long flags;
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pr_debug("m32r_cfc: pcc_iowrite_word: sock=%d, port=%#lx, "
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"buf=%p, size=%u, nmemb=%d, flag=%d\n",
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sock, port, buf, size, nmemb, flag);
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if(size != 2)
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printk("m32r_cfc: iowrite_word :illigal size %u : %#lx\n",
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size, port);
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if(size == 9)
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printk("m32r_cfc: iowrite_word :outsw \n");
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addr = pcc_port2addr(port, 2);
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if (!addr) {
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printk("m32r_cfc:iowrite_word null addr :%#lx\n",port);
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return;
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}
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#if 1
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if (addr & 1) {
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printk("m32r_cfc:iowrite_word port addr (%#lx):%#lx\n", port,
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addr);
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return;
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}
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#endif
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pr_debug("m32r_cfc: pcc_iowrite_word: addr=%#lx\n", addr);
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spin_lock_irqsave(&pcc_lock, flags);
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while (nmemb--)
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writew(*bp++, addr);
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spin_unlock_irqrestore(&pcc_lock, flags);
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}
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/*====================================================================*/
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#define IS_REGISTERED 0x2000
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#define IS_ALIVE 0x8000
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typedef struct pcc_t {
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char *name;
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u_short flags;
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} pcc_t;
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static pcc_t pcc[] = {
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#if !defined(CONFIG_PLAT_USRV)
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{ "m32r_cfc", 0 }, { "", 0 },
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#else /* CONFIG_PLAT_USRV */
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{ "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "m32r_cfc", 0 },
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{ "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "", 0 },
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#endif /* CONFIG_PLAT_USRV */
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};
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static irqreturn_t pcc_interrupt(int, void *);
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/*====================================================================*/
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static struct timer_list poll_timer;
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static unsigned int pcc_get(u_short sock, unsigned int reg)
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{
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unsigned int val = inw(reg);
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pr_debug("m32r_cfc: pcc_get: reg(0x%08x)=0x%04x\n", reg, val);
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return val;
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}
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static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
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{
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outw(data, reg);
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pr_debug("m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data);
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}
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/*======================================================================
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See if a card is present, powered up, in IO mode, and already
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bound to a (non PC Card) Linux driver. We leave these alone.
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We make an exception for cards that seem to be serial devices.
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======================================================================*/
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static int __init is_alive(u_short sock)
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{
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unsigned int stat;
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pr_debug("m32r_cfc: is_alive:\n");
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printk("CF: ");
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stat = pcc_get(sock, (unsigned int)PLD_CFSTS);
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if (!stat)
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printk("No ");
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printk("Card is detected at socket %d : stat = 0x%08x\n", sock, stat);
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pr_debug("m32r_cfc: is_alive: sock stat is 0x%04x\n", stat);
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return 0;
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}
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static void add_pcc_socket(ulong base, int irq, ulong mapaddr,
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unsigned int ioaddr)
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{
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pcc_socket_t *t = &socket[pcc_sockets];
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pr_debug("m32r_cfc: add_pcc_socket: base=%#lx, irq=%d, "
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"mapaddr=%#lx, ioaddr=%08x\n",
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base, irq, mapaddr, ioaddr);
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/* add sockets */
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t->ioaddr = ioaddr;
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t->mapaddr = mapaddr;
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#if !defined(CONFIG_PLAT_USRV)
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t->base = 0;
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t->flags = 0;
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t->cs_irq1 = irq; // insert irq
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t->cs_irq2 = irq + 1; // eject irq
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#else /* CONFIG_PLAT_USRV */
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t->base = base;
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t->flags = 0;
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t->cs_irq1 = 0; // insert irq
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t->cs_irq2 = 0; // eject irq
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#endif /* CONFIG_PLAT_USRV */
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if (is_alive(pcc_sockets))
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t->flags |= IS_ALIVE;
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/* add pcc */
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#if !defined(CONFIG_PLAT_USRV)
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request_region((unsigned int)PLD_CFRSTCR, 0x20, "m32r_cfc");
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#else /* CONFIG_PLAT_USRV */
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{
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unsigned int reg_base;
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reg_base = (unsigned int)PLD_CFRSTCR;
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reg_base |= pcc_sockets << 8;
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request_region(reg_base, 0x20, "m32r_cfc");
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}
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#endif /* CONFIG_PLAT_USRV */
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printk(KERN_INFO " %s ", pcc[pcc_sockets].name);
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printk("pcc at 0x%08lx\n", t->base);
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/* Update socket interrupt information, capabilities */
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t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
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t->socket.map_size = M32R_PCC_MAPSIZE;
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t->socket.io_offset = ioaddr; /* use for io access offset */
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t->socket.irq_mask = 0;
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#if !defined(CONFIG_PLAT_USRV)
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t->socket.pci_irq = PLD_IRQ_CFIREQ ; /* card interrupt */
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#else /* CONFIG_PLAT_USRV */
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t->socket.pci_irq = PLD_IRQ_CF0 + pcc_sockets;
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#endif /* CONFIG_PLAT_USRV */
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#ifndef CONFIG_PLAT_USRV
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/* insert interrupt */
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request_irq(irq, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
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#ifndef CONFIG_PLAT_MAPPI3
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/* eject interrupt */
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request_irq(irq+1, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
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#endif
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pr_debug("m32r_cfc: enable CFMSK, RDYSEL\n");
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pcc_set(pcc_sockets, (unsigned int)PLD_CFIMASK, 0x01);
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#endif /* CONFIG_PLAT_USRV */
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#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
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pcc_set(pcc_sockets, (unsigned int)PLD_CFCR1, 0x0200);
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#endif
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pcc_sockets++;
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return;
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}
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/*====================================================================*/
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static irqreturn_t pcc_interrupt(int irq, void *dev)
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{
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int i;
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u_int events = 0;
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int handled = 0;
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pr_debug("m32r_cfc: pcc_interrupt: irq=%d, dev=%p\n", irq, dev);
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for (i = 0; i < pcc_sockets; i++) {
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if (socket[i].cs_irq1 != irq && socket[i].cs_irq2 != irq)
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continue;
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handled = 1;
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pr_debug("m32r_cfc: pcc_interrupt: socket %d irq 0x%02x ",
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i, irq);
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events |= SS_DETECT; /* insert or eject */
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if (events)
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pcmcia_parse_events(&socket[i].socket, events);
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}
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pr_debug("m32r_cfc: pcc_interrupt: done\n");
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return IRQ_RETVAL(handled);
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} /* pcc_interrupt */
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static void pcc_interrupt_wrapper(u_long data)
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{
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pr_debug("m32r_cfc: pcc_interrupt_wrapper:\n");
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pcc_interrupt(0, NULL);
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init_timer(&poll_timer);
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poll_timer.expires = jiffies + poll_interval;
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add_timer(&poll_timer);
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}
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/*====================================================================*/
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static int _pcc_get_status(u_short sock, u_int *value)
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{
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u_int status;
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pr_debug("m32r_cfc: _pcc_get_status:\n");
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status = pcc_get(sock, (unsigned int)PLD_CFSTS);
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*value = (status) ? SS_DETECT : 0;
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pr_debug("m32r_cfc: _pcc_get_status: status=0x%08x\n", status);
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#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
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if ( status ) {
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/* enable CF power */
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status = inw((unsigned int)PLD_CPCR);
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if (!(status & PLD_CPCR_CF)) {
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pr_debug("m32r_cfc: _pcc_get_status: "
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"power on (CPCR=0x%08x)\n", status);
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status |= PLD_CPCR_CF;
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outw(status, (unsigned int)PLD_CPCR);
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udelay(100);
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}
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*value |= SS_POWERON;
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pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */
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udelay(100);
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*value |= SS_READY; /* always ready */
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*value |= SS_3VCARD;
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} else {
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/* disable CF power */
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status = inw((unsigned int)PLD_CPCR);
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status &= ~PLD_CPCR_CF;
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outw(status, (unsigned int)PLD_CPCR);
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udelay(100);
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pr_debug("m32r_cfc: _pcc_get_status: "
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"power off (CPCR=0x%08x)\n", status);
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}
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#elif defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
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if ( status ) {
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status = pcc_get(sock, (unsigned int)PLD_CPCR);
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if (status == 0) { /* power off */
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pcc_set(sock, (unsigned int)PLD_CPCR, 1);
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pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */
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udelay(50);
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}
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*value |= SS_POWERON;
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pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);
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udelay(50);
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pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101);
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udelay(25); /* for IDE reset */
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pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100);
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mdelay(2); /* for IDE reset */
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*value |= SS_READY;
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*value |= SS_3VCARD;
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} else {
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/* disable CF power */
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pcc_set(sock, (unsigned int)PLD_CPCR, 0);
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udelay(100);
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pr_debug("m32r_cfc: _pcc_get_status: "
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"power off (CPCR=0x%08x)\n", status);
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}
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#else
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#error no platform configuration
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#endif
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pr_debug("m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n",
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sock, *value);
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return 0;
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} /* _get_status */
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/*====================================================================*/
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static int _pcc_set_socket(u_short sock, socket_state_t *state)
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{
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pr_debug("m32r_cfc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
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"io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
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state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
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#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
|
|
if (state->Vcc) {
|
|
if ((state->Vcc != 50) && (state->Vcc != 33))
|
|
return -EINVAL;
|
|
/* accept 5V and 3.3V */
|
|
}
|
|
#endif
|
|
if (state->flags & SS_RESET) {
|
|
pr_debug(":RESET\n");
|
|
pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x101);
|
|
}else{
|
|
pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x100);
|
|
}
|
|
if (state->flags & SS_OUTPUT_ENA){
|
|
pr_debug(":OUTPUT_ENA\n");
|
|
/* bit clear */
|
|
pcc_set(sock,(unsigned int)PLD_CFBUFCR,0);
|
|
} else {
|
|
pcc_set(sock,(unsigned int)PLD_CFBUFCR,1);
|
|
}
|
|
|
|
if(state->flags & SS_IOCARD){
|
|
pr_debug(":IOCARD");
|
|
}
|
|
if (state->flags & SS_PWR_AUTO) {
|
|
pr_debug(":PWR_AUTO");
|
|
}
|
|
if (state->csc_mask & SS_DETECT)
|
|
pr_debug(":csc-SS_DETECT");
|
|
if (state->flags & SS_IOCARD) {
|
|
if (state->csc_mask & SS_STSCHG)
|
|
pr_debug(":STSCHG");
|
|
} else {
|
|
if (state->csc_mask & SS_BATDEAD)
|
|
pr_debug(":BATDEAD");
|
|
if (state->csc_mask & SS_BATWARN)
|
|
pr_debug(":BATWARN");
|
|
if (state->csc_mask & SS_READY)
|
|
pr_debug(":READY");
|
|
}
|
|
pr_debug("\n");
|
|
return 0;
|
|
} /* _set_socket */
|
|
|
|
/*====================================================================*/
|
|
|
|
static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
|
|
{
|
|
u_char map;
|
|
|
|
pr_debug("m32r_cfc: SetIOMap(%d, %d, %#2.2x, %d ns, "
|
|
"%#llx-%#llx)\n", sock, io->map, io->flags,
|
|
io->speed, (unsigned long long)io->start,
|
|
(unsigned long long)io->stop);
|
|
map = io->map;
|
|
|
|
return 0;
|
|
} /* _set_io_map */
|
|
|
|
/*====================================================================*/
|
|
|
|
static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
|
|
{
|
|
|
|
u_char map = mem->map;
|
|
u_long addr;
|
|
pcc_socket_t *t = &socket[sock];
|
|
|
|
pr_debug("m32r_cfc: SetMemMap(%d, %d, %#2.2x, %d ns, "
|
|
"%#llx, %#x)\n", sock, map, mem->flags,
|
|
mem->speed, (unsigned long long)mem->static_start,
|
|
mem->card_start);
|
|
|
|
/*
|
|
* sanity check
|
|
*/
|
|
if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* de-activate
|
|
*/
|
|
if ((mem->flags & MAP_ACTIVE) == 0) {
|
|
t->current_space = as_none;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Set mode
|
|
*/
|
|
if (mem->flags & MAP_ATTRIB) {
|
|
t->current_space = as_attr;
|
|
} else {
|
|
t->current_space = as_comm;
|
|
}
|
|
|
|
/*
|
|
* Set address
|
|
*/
|
|
addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
|
|
mem->static_start = addr + mem->card_start;
|
|
|
|
return 0;
|
|
|
|
} /* _set_mem_map */
|
|
|
|
#if 0 /* driver model ordering issue */
|
|
/*======================================================================
|
|
|
|
Routines for accessing socket information and register dumps via
|
|
/proc/bus/pccard/...
|
|
|
|
======================================================================*/
|
|
|
|
static ssize_t show_info(struct class_device *class_dev, char *buf)
|
|
{
|
|
pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
|
|
socket.dev);
|
|
|
|
return sprintf(buf, "type: %s\nbase addr: 0x%08lx\n",
|
|
pcc[s->type].name, s->base);
|
|
}
|
|
|
|
static ssize_t show_exca(struct class_device *class_dev, char *buf)
|
|
{
|
|
/* FIXME */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
|
|
static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
|
|
#endif
|
|
|
|
/*====================================================================*/
|
|
|
|
/* this is horribly ugly... proper locking needs to be done here at
|
|
* some time... */
|
|
#define LOCKED(x) do { \
|
|
int retval; \
|
|
unsigned long flags; \
|
|
spin_lock_irqsave(&pcc_lock, flags); \
|
|
retval = x; \
|
|
spin_unlock_irqrestore(&pcc_lock, flags); \
|
|
return retval; \
|
|
} while (0)
|
|
|
|
|
|
static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
|
|
{
|
|
unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
|
|
|
|
if (socket[sock].flags & IS_ALIVE) {
|
|
dev_dbg(&s->dev, "pcc_get_status: sock(%d) -EINVAL\n", sock);
|
|
*value = 0;
|
|
return -EINVAL;
|
|
}
|
|
dev_dbg(&s->dev, "pcc_get_status: sock(%d)\n", sock);
|
|
LOCKED(_pcc_get_status(sock, value));
|
|
}
|
|
|
|
static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
|
|
{
|
|
unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
|
|
|
|
if (socket[sock].flags & IS_ALIVE) {
|
|
dev_dbg(&s->dev, "pcc_set_socket: sock(%d) -EINVAL\n", sock);
|
|
return -EINVAL;
|
|
}
|
|
dev_dbg(&s->dev, "pcc_set_socket: sock(%d)\n", sock);
|
|
LOCKED(_pcc_set_socket(sock, state));
|
|
}
|
|
|
|
static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
|
|
{
|
|
unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
|
|
|
|
if (socket[sock].flags & IS_ALIVE) {
|
|
dev_dbg(&s->dev, "pcc_set_io_map: sock(%d) -EINVAL\n", sock);
|
|
return -EINVAL;
|
|
}
|
|
dev_dbg(&s->dev, "pcc_set_io_map: sock(%d)\n", sock);
|
|
LOCKED(_pcc_set_io_map(sock, io));
|
|
}
|
|
|
|
static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
|
|
{
|
|
unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
|
|
|
|
if (socket[sock].flags & IS_ALIVE) {
|
|
dev_dbg(&s->dev, "pcc_set_mem_map: sock(%d) -EINVAL\n", sock);
|
|
return -EINVAL;
|
|
}
|
|
dev_dbg(&s->dev, "pcc_set_mem_map: sock(%d)\n", sock);
|
|
LOCKED(_pcc_set_mem_map(sock, mem));
|
|
}
|
|
|
|
static int pcc_init(struct pcmcia_socket *s)
|
|
{
|
|
dev_dbg(&s->dev, "pcc_init()\n");
|
|
return 0;
|
|
}
|
|
|
|
static struct pccard_operations pcc_operations = {
|
|
.init = pcc_init,
|
|
.get_status = pcc_get_status,
|
|
.set_socket = pcc_set_socket,
|
|
.set_io_map = pcc_set_io_map,
|
|
.set_mem_map = pcc_set_mem_map,
|
|
};
|
|
|
|
|
|
/*====================================================================*/
|
|
|
|
static struct platform_driver pcc_driver = {
|
|
.driver = {
|
|
.name = "cfc",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static struct platform_device pcc_device = {
|
|
.name = "cfc",
|
|
.id = 0,
|
|
};
|
|
|
|
/*====================================================================*/
|
|
|
|
static int __init init_m32r_pcc(void)
|
|
{
|
|
int i, ret;
|
|
|
|
ret = platform_driver_register(&pcc_driver);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = platform_device_register(&pcc_device);
|
|
if (ret){
|
|
platform_driver_unregister(&pcc_driver);
|
|
return ret;
|
|
}
|
|
|
|
#if defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
|
|
pcc_set(0, (unsigned int)PLD_CFCR0, 0x0f0f);
|
|
pcc_set(0, (unsigned int)PLD_CFCR1, 0x0200);
|
|
#endif
|
|
|
|
pcc_sockets = 0;
|
|
|
|
#if !defined(CONFIG_PLAT_USRV)
|
|
add_pcc_socket(M32R_PCC0_BASE, PLD_IRQ_CFC_INSERT, CFC_ATTR_MAPBASE,
|
|
CFC_IOPORT_BASE);
|
|
#else /* CONFIG_PLAT_USRV */
|
|
{
|
|
ulong base, mapaddr;
|
|
unsigned int ioaddr;
|
|
|
|
for (i = 0 ; i < M32R_MAX_PCC ; i++) {
|
|
base = (ulong)PLD_CFRSTCR;
|
|
base = base | (i << 8);
|
|
ioaddr = (i + 1) << 12;
|
|
mapaddr = CFC_ATTR_MAPBASE | (i << 20);
|
|
add_pcc_socket(base, 0, mapaddr, ioaddr);
|
|
}
|
|
}
|
|
#endif /* CONFIG_PLAT_USRV */
|
|
|
|
if (pcc_sockets == 0) {
|
|
printk("socket is not found.\n");
|
|
platform_device_unregister(&pcc_device);
|
|
platform_driver_unregister(&pcc_driver);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Set up interrupt handler(s) */
|
|
|
|
for (i = 0 ; i < pcc_sockets ; i++) {
|
|
socket[i].socket.dev.parent = &pcc_device.dev;
|
|
socket[i].socket.ops = &pcc_operations;
|
|
socket[i].socket.resource_ops = &pccard_static_ops;
|
|
socket[i].socket.owner = THIS_MODULE;
|
|
socket[i].number = i;
|
|
ret = pcmcia_register_socket(&socket[i].socket);
|
|
if (!ret)
|
|
socket[i].flags |= IS_REGISTERED;
|
|
|
|
#if 0 /* driver model ordering issue */
|
|
class_device_create_file(&socket[i].socket.dev,
|
|
&class_device_attr_info);
|
|
class_device_create_file(&socket[i].socket.dev,
|
|
&class_device_attr_exca);
|
|
#endif
|
|
}
|
|
|
|
/* Finally, schedule a polling interrupt */
|
|
if (poll_interval != 0) {
|
|
poll_timer.function = pcc_interrupt_wrapper;
|
|
poll_timer.data = 0;
|
|
init_timer(&poll_timer);
|
|
poll_timer.expires = jiffies + poll_interval;
|
|
add_timer(&poll_timer);
|
|
}
|
|
|
|
return 0;
|
|
} /* init_m32r_pcc */
|
|
|
|
static void __exit exit_m32r_pcc(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < pcc_sockets; i++)
|
|
if (socket[i].flags & IS_REGISTERED)
|
|
pcmcia_unregister_socket(&socket[i].socket);
|
|
|
|
platform_device_unregister(&pcc_device);
|
|
if (poll_interval != 0)
|
|
del_timer_sync(&poll_timer);
|
|
|
|
platform_driver_unregister(&pcc_driver);
|
|
} /* exit_m32r_pcc */
|
|
|
|
module_init(init_m32r_pcc);
|
|
module_exit(exit_m32r_pcc);
|
|
MODULE_LICENSE("Dual MPL/GPL");
|
|
/*====================================================================*/
|