933 lines
33 KiB
C
Executable File
933 lines
33 KiB
C
Executable File
/*
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* SPIFLASH support for TC3162
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*/
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/*
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* SPI Flash Memory support header file.
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*
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* Copyright (c) 2005, Atheros Communications Inc.
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* Copyright (C) 2006 FON Technology, SL.
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* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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*
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* This code is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __NEWSPIFLASH_H
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#define __NEWSPIFLASH_H
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#define SF_BASE 0xBFA10000
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#define SF_READ_MODE (SF_BASE + 0x0000)
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#define SF_READ_IDLE_EN (SF_BASE + 0x0004)
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#define SF_SIDLY (SF_BASE + 0x0008)
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#define SF_CSHEXT (SF_BASE + 0x000C)
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#define SF_CSLEXT (SF_BASE + 0x0010)
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#define SF_MTX_MODE_TOG (SF_BASE + 0x0014)
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#define SF_RDCTL_FSM (SF_BASE + 0x0018)
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#define SF_MACMUX_SEL (SF_BASE + 0x001C)
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#define SF_MANUAL_EN (SF_BASE + 0x0020)
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#define SF_MANUAL_OPFIFO_EMPTY (SF_BASE + 0x0024)
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#define SF_MANUAL_OPFIFO_WDATA (SF_BASE + 0x0028)
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#define SF_MANUAL_OPFIFO_FULL (SF_BASE + 0x002C)
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#define SF_MANUAL_OPFIFO_WR (SF_BASE + 0x0030)
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#define SF_MANUAL_DFIFO_FULL (SF_BASE + 0x0034)
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#define SF_MANUAL_DFIFO_WDATA (SF_BASE + 0x0038)
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#define SF_MANUAL_DFIFO_EMPTY (SF_BASE + 0x003C)
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#define SF_MANUAL_DFIFO_RD (SF_BASE + 0x0040)
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#define SF_MANUAL_DFIFO_RDATA (SF_BASE + 0x0044)
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#define SF_DUMMY (SF_BASE + 0x0080)
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#define SF_ADDR_3B4B (SF_BASE + 0x0084)
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#define SF_PROBE_SEL (SF_BASE + 0x0088)
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#define SF_CFG3B4B_EN (SF_BASE + 0x008C)
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#define SF_INTERRUPT (SF_BASE + 0x0090)
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#define SF_INTERRUPT_EN (SF_BASE + 0x0094)
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#define SF_SI_CK_SEL (SF_BASE + 0x009C)
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#define SF_CLK_CHANGE 0xBFA20068
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#define SF_READ_MODE_VALUE VPint(SF_READ_MODE)
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#define SF_READ_IDLE_EN_VALUE VPint(SF_READ_IDLE_EN)
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#define SF_SIDLY_VALUE VPint(SF_SIDLY)
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#define SF_CSHEXT_VALUE VPint(SF_CSHEXT)
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#define SF_CSLEXT_VALUE VPint(SF_CSLEXT)
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#define SF_MTX_MODE_TOG_VALUE VPint(SF_MTX_MODE_TOG)
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#define SF_RDCTL_FSM_VALUE VPint(SF_RDCTL_FSM)
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#define SF_MACMUX_SEL_VALUE VPint(SF_MACMUX_SEL)
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#define SF_MANUAL_EN_VALUE VPint(SF_MANUAL_EN)
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#define SF_MANUAL_OPFIFO_EMPTY_VALUE VPint(SF_MANUAL_OPFIFO_EMPTY)
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#define SF_MANUAL_OPFIFO_WDATA_VALUE VPint(SF_MANUAL_OPFIFO_WDATA)
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#define SF_MANUAL_OPFIFO_FULL_VALUE VPint(SF_MANUAL_OPFIFO_FULL)
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#define SF_MANUAL_OPFIFO_WR_VALUE VPint(SF_MANUAL_OPFIFO_WR)
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#define SF_MANUAL_DFIFO_FULL_VALUE VPint(SF_MANUAL_DFIFO_FULL)
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#define SF_MANUAL_DFIFO_WDATA_VALUE VPint(SF_MANUAL_DFIFO_WDATA)
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#define SF_MANUAL_DFIFO_EMPTY_VALUE VPint(SF_MANUAL_DFIFO_EMPTY)
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#define SF_MANUAL_DFIFO_RD_VALUE VPint(SF_MANUAL_DFIFO_RD)
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#define SF_MANUAL_DFIFO_RDATA_VALUE VPint(SF_MANUAL_DFIFO_RDATA)
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#define SF_DUMMY_VALUE VPint(SF_DUMMY)
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#define SF_ADDR_3B4B_VALUE VPint(SF_ADDR_3B4B)
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#define SF_PROBE_SEL_VALUE VPint(SF_PROBE_SEL)
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#define SF_CFG3B4B_EN_VALUE VPint(SF_CFG3B4B_EN)
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#define SF_INTERRUPT_VALUE VPint(SF_INTERRUPT)
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#define SF_INTERRUPT_EN_VALUE VPint(SF_INTERRUPT_EN)
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#define SF_SI_CK_SEL_VALUE VPint(SF_SI_CK_SEL)
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#define SF_CLK_CHANGE_VALUE VPint(SF_CLK_CHANGE)
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#define SF_OP_WR_ENABLE 0x06 /* Write Enable */
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#define SF_OP_WR_DISABLE 0x04 /* Write Disable */
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#define SF_OP_RD_STATUS1 0x05 /* Read Status 1 */
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#define SF_OP_WR_STATUS1 0x01 /* Write Status 1 */
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#define SF_OP_RD_STATUS2 0x35 /* Read Status 2 */
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#define SF_OP_WR_STATUS2 0x31 /* Write Status 2 */
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#define SF_OP_RD_STATUS3 0x15 /* Read Status 3 */
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#define SF_OP_WR_STATUS3 0x11 /* Write Status 3 */
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#define SF_OP_RD_STATUSEX 0xC8 /* Read extend Status */ // only for W25Q256 & N25Q256
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#define SF_OP_WR_STATUSEX 0xC5 /* Write extend Status */ // only for W25Q256 & N25Q256
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#define SF_OP_RD_BANKREG 0x16 /* Read Bank Register */ // only for S25FL256S
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#define SF_OP_WR_BANKREG 0x17 /* Write Bank Register */ // only for S25FL256S
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#define SF_OP_RD_ENHANCED_CFGREG 0x65 /* Read Enhanced Register */ // only for N25Q256
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#define SF_OP_WR_ENHANCED_CFGREG 0x61 /* Write Enhanced Register */ // only for N25Q256
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#define SF_OP_RD_VOLATILE_CFGREG 0x85 /* Read Volatile Register */ // only for N25Q256
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#define SF_OP_WR_VOLATILE_CFGREG 0x81 /* Write Volatile Register */ // only for N25Q256
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#define SF_OP_RD_NONVOLATILE_CFGREG 0xB5 /* Read Non-Volatile Register */ // only for N25Q256
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#define SF_OP_WR_NONVOLATILE_CFGREG 0xB1 /* Write Non-Volatile Register */ // only for N25Q256
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#define SF_OP_RD_DATA 0x03 /* Read Data */
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#define SF_OP_FAST_RD_DATA 0x0B /* Fast Read Data */
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#define SF_OP_FAST_RD_DUAL_OUT 0x3B /* Fast Read Data Dual Output */
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#define SF_OP_FAST_RD_DUAL_IO 0xBB /* Fast Read Data Dual I/O */
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#define SF_OP_PAGE_PROGRAM 0x02 /* Page Program */
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#define SF_OP_SECTOR_ERASE 0xD8 /* Sector Erase */
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#define SF_OP_BULK_ERASE 0xC7 /* Bulk Erase */
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#define SF_OP_4BYTES_RD_DATA 0x13 /* Read Data in 4Bytes Address */
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#define SF_OP_4BYTES_FAST_RD_DATA 0x0C /* Fast Read Data in 4Bytes Address */
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#define SF_OP_4BYTES_FAST_RD_DUAL_OUT 0x3C /* Fast Read Data Dual Output in 4Bytes Address */
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#define SF_OP_4BYTES_FAST_RD_DUAL_IO 0xBC /* Fast Read Data Dual I/O in 4Bytes Address */
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#define SF_OP_4BYTES_PAGE_PROGRAM 0x12 /* Page Program in 4Bytes Address */
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#define SF_OP_4BYTES_SECTOR_ERASE 0xDC /* Sector Erase in 4Bytes Address */
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#define SF_OP_ENTER_4BYTES_MODE 0xB7 /* enter 4bytes address mode */
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#define SF_OP_EXIT_4BYTES_MODE 0xE9 /* exit 4bytes address mode */
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#define SF_OP_POWER_DOWN 0xB9 /* Power Down to reduce power */
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#define SF_OP_RELEASE_POWER_DOWN 0xAB /* release power down */
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#define SF_OP_RD_ID 0x9F /* Read JEDEC ID */
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#define SF_STATUS_WIP 0x01 /* Write-In-Progress */
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#define SF_STATUS_WEL 0x02 /* Write Enable Latch */
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#define SF_STATUS_BP0 0x04 /* Block Protect 0 */
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#define SF_STATUS_BP1 0x08 /* Block Protect 1 */
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#define SF_STATUS_BP2 0x10 /* Block Protect 2 */
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#define SF_STATUS_SRWD 0x80 /* Status Register Write Disable */
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#define SF_STATUS_QE 0x02 /* Quad Enable */
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#define OP_CSH 0x00
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#define OP_CSL 0x01
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#define OP_CK 0x02
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#define OP_OUTS 0x08
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#define OP_OUTD 0x09
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#define OP_OUTQ 0x0A
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#define OP_INS 0x0C
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#define OP_INS0 0x0D
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#define OP_IND 0x0E
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#define OP_INQ 0x0F
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#define OP_OS2IS 0x10
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#define OP_OS2ID 0x11
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#define OP_OS2IQ 0x12
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#define OP_OD2IS 0x13
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#define OP_OD2ID 0x14
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#define OP_OD2IQ 0x15
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#define OP_OQ2IS 0x16
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#define OP_OQ2ID 0x17
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#define OP_OQ2IQ 0x18
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#define OP_OSNIS 0x19
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#define OP_ODNID 0x1A
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#define OP_SHIFT (9)
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#define OP_REPEAT_ONE (1)
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#define OP_REPEAT_TWO (2)
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#define OP_REPEAT_THREE (3)
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#define OP_REPEAT_FOUR (4)
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#define OP_REPEAT_FIVE (5)
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#define OP_ENABLE (1)
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#define OP_DISABLE (0)
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#define OP_CMD_MASK (0x1f)
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#define OP_LEN_MASK (0x1ff)
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#define SF_RD_MAX (0x100)//(0x1ff)
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#define SF_PP_MAX (0x100)
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#define DDATA_ENABLE (1)
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#define DDATA_DISABLE (0)
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#define DDATA_MASK (0xff)
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#define SI_SEL_MASK (0x7)
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#define DUMMY_DATA 0x0
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#define AUTO_MTXMODE 0x0
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#define AUTO_MANUALEN 0x0
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#define MANUAL_MTXMODE 0x9
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#define MANUAL_MANUALEN 0x1
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#define MANUAL_MACMUXSEL 0x1
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#define READ_DATA 0x0
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#define FAST_READ 0x1
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#define FAST_READ_DUALOUT 0x2
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#define FAST_READ_DUALIO 0x3
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#define CFG3B4B_DIS (0)
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#define CFG3B4B_EN (1)
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#define AUTO_3BMODE (0)
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#define AUTO_4BMODE (1)
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#define RD_IDLE_DIS (0)
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#define RD_IDLE_EN (1)
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#define CUR_AUTO_MODE (0)
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#define CUR_MANUAL_MODE (1)
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#define EXTSYNC_RFIFO_UNF_INTR_EN (0x100)
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#define EXTSYNC_RFIFO_OVF_INTR_EN (0x80)
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#define EXTSYNC_TPFIFO_UNF_INTR_EN (0x40)
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#define EXTSYNC_TPFIFO_OVF_INTR_EN (0x20)
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#define MANUAL_DFIFO_UNF_INTR_EN (0x10)
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#define MANUAL_DFIFO_OVF_INTR_EN (0x8)
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#define MANUAL_OPFIFO_UNF_INTR_EN (0x4)
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#define MANUAL_OPFIFO_OVF_INTR_EN (0x2)
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#define AUTO_MANUAL_INTR_EN (0x1)
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#define AUTO_READ (0)
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#define AUTO_FAST_READ (1)
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#define AUTO_FAST_READ_DUALOUT (2)
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#define AUTO_FAST_READ_DUALIO (3)
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#define SF_SR1_DEFAULT 0x0
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#define SF_SR2_DEFAULT 0x0
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#define SF_BANKREG_3B 0x0
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#define SF_BANKREG_4B 0x80
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#define WriteReg(reg, data) (VPint(reg) = data)
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#define ReadReg(reg) (VPint(reg))
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#define bReadReg(reg, mask) (VPint(reg) & mask)
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#define wLoWord(data) ((data) & 0xffff)
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#define wHiWord(data) (((data)>>16) & 0xffff)
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#define bLoByte(data) ((data) & 0xff)
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#define bHiByte(data) (((data)>>8) & 0xff)
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// Send change sf clk to 25MHZ command
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#define SEND_CLK_25MHZ_CMD \
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{ \
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/* change sf clk to 25MHZ */ \
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WriteReg(SF_CLK_CHANGE, 6); \
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}
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// Send change sf clk to 50MHZ command
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#define SEND_CLK_50MHZ_CMD \
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{ \
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/* change sf clk to 50MHZ */ \
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WriteReg(SF_CLK_CHANGE, 3); \
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}
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// Send opfifo write command
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#define SEND_OPFIFO_WRITE_CMD(op_cmd, op_len) \
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{ \
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/* write op_cmd to register OPFIFO_WDATA */ \
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WriteReg(SF_MANUAL_OPFIFO_WDATA, ((((op_cmd) & OP_CMD_MASK) << OP_SHIFT) | ((op_len) & OP_LEN_MASK))); \
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/* wait until opfifo is not full */ \
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while(ReadReg(SF_MANUAL_OPFIFO_FULL)) ; \
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/* enable write from register OPFIFO_WDATA to opfifo */ \
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WriteReg(SF_MANUAL_OPFIFO_WR, OP_ENABLE); \
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/* wait until opfifo is empty */ \
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while(!ReadReg(SF_MANUAL_OPFIFO_EMPTY)); \
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}
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// Send dfifo write command
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// Parameters:
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// data: type is char
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#define SEND_DFIFO_WRITE_CMD(data) \
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{ \
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/* wait until dfifo is not full */ \
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while(ReadReg(SF_MANUAL_DFIFO_FULL)) ; \
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/* write data to register DFIFO_WDATA */ \
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WriteReg(SF_MANUAL_DFIFO_WDATA, ((data) & DDATA_MASK)); \
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}
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// Send dfifo read command
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// Parameters:
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// data: type is char
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#define SEND_DFIFO_READ_CMD(data) \
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{ \
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/* wait until dfifo is not empty */ \
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while(ReadReg(SF_MANUAL_DFIFO_EMPTY)) ; \
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/* read from dfifo to register DFIFO_RDATA */ \
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(data) = ReadReg(SF_MANUAL_DFIFO_RDATA); \
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/* enable register DFIFO_RD to read next byte */ \
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WriteReg(SF_MANUAL_DFIFO_RD, DDATA_ENABLE); \
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}
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// Send manual mode begin command
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#define SEND_MANUAL_BEGIN_CMD \
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{ \
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sf_manual_begin(); \
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}
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// Send manual mode end command
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#define SEND_MANUAL_END_CMD \
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{ \
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sf_manual_end(); \
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}
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// Send manual mode begin command
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#define SEND_MANUAL_WREN_BEGIN_CMD \
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{ \
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sf_manual_wren_begin(); \
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}
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// Send manual mode end command
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#define SEND_MANUAL_WREN_END_CMD \
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{ \
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sf_manual_wren_end(); \
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}
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// Send CSL command
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#define SEND_CSL_CMD \
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{ \
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SEND_OPFIFO_WRITE_CMD(OP_CSL, OP_REPEAT_ONE) \
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SEND_OPFIFO_WRITE_CMD(OP_CSL, OP_REPEAT_ONE) \
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}
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// Send CSH command
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#define SEND_CSH_CMD \
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{ \
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SEND_OPFIFO_WRITE_CMD(OP_CSH, OP_REPEAT_ONE) \
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SEND_OPFIFO_WRITE_CMD(OP_CK, OP_REPEAT_FIVE) \
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}
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// Send write enable command
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#define SEND_WREN_CMD \
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{ \
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send_single_opcode_cmd(SF_OP_WR_ENABLE); \
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}
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// Send write disable command
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#define SEND_WRDIS_CMD \
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{ \
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SEND_MANUAL_BEGIN_CMD \
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send_single_opcode_cmd(SF_OP_WR_DISABLE); \
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SEND_MANUAL_END_CMD \
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}
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// Send read register internal command
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// Parameters:
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// data: type is char
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#define SEND_READ_REGISTER_INTERNAL_CMD(op_cmd, data) \
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{ \
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SEND_CSL_CMD \
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/* write op_cmd */ \
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SEND_OPFIFO_WRITE_CMD(OP_OS2IS, OP_REPEAT_ONE) \
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SEND_DFIFO_WRITE_CMD(op_cmd) \
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/* read register */ \
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SEND_OPFIFO_WRITE_CMD(OP_INS, OP_REPEAT_ONE) \
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SEND_DFIFO_READ_CMD(data) \
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SEND_CSH_CMD \
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}
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// Send general read register command
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// Parameters:
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// data: type is char
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#define SEND_READ_REGISTER_CMD(op_cmd, data) \
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{ \
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SEND_MANUAL_BEGIN_CMD \
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SEND_READ_REGISTER_INTERNAL_CMD(op_cmd, data) \
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SEND_MANUAL_END_CMD \
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}
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// Send write register internal command
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// Parameters:
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// data: type is char
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#define SEND_WRITE_REGISTER_INTERNAL_CMD(op_cmd, data) \
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{ \
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SEND_CSL_CMD \
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/* write op_cmd */ \
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SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_ONE) \
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SEND_DFIFO_WRITE_CMD(op_cmd) \
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/* write register */ \
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SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_ONE) \
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SEND_DFIFO_WRITE_CMD(data) \
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SEND_CSH_CMD \
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}
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// Send general write register command
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// Parameters:
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// data: type is char
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#define SEND_WRITE_REGISTER_CMD(op_cmd, data) \
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{ \
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SEND_MANUAL_WREN_BEGIN_CMD \
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SEND_WRITE_REGISTER_INTERNAL_CMD(op_cmd, data) \
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SEND_MANUAL_WREN_END_CMD \
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}
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// Send wait WIP bit idle command
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// Parameters:
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// reg_val: type is char
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#define SEND_WAIT_WIP_IDLE_INTERNAL_CMD(reg_val) \
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{ \
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do { \
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SEND_READ_REGISTER_INTERNAL_CMD(SF_OP_RD_STATUS1, reg_val) \
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} while (reg_val & SF_STATUS_WIP); \
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}
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// Send read data command
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// Parameters:
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// dAddr: 3bytes or 4bytes length, depend the value of mode
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// data: type is char*
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// len: the value is [1, FlashSize-1]
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// mode: 1 means 4bytes, 0 means 3bytes
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#define SEND_READ_CMD(dAddr, data, len, mode) \
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{ \
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SEND_MANUAL_BEGIN_CMD \
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SEND_CSL_CMD \
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/* write op_cmd 0x03 */ \
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SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_ONE) \
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SEND_DFIFO_WRITE_CMD(SF_OP_RD_DATA) \
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/* write address */ \
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SEND_OPFIFO_WRITE_CMD(OP_OUTS, ((mode)?0x03:0x02)) \
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if(mode){ \
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SEND_DFIFO_WRITE_CMD(bHiByte(wHiWord(dAddr))) \
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} \
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SEND_DFIFO_WRITE_CMD(bLoByte(wHiWord(dAddr))) \
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SEND_DFIFO_WRITE_CMD(bHiByte(wLoWord(dAddr))) \
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SEND_OPFIFO_WRITE_CMD(OP_OS2IS, OP_REPEAT_ONE) \
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SEND_DFIFO_WRITE_CMD(bLoByte(wLoWord(dAddr))) \
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/* read data */ \
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while((len) > 0) { \
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if((len) % SF_RD_MAX) { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_INS, ((len)%SF_RD_MAX)) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} else { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_INS, SF_RD_MAX) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} \
|
|
} \
|
|
SEND_CSH_CMD \
|
|
SEND_MANUAL_END_CMD \
|
|
}
|
|
|
|
// Send fast read command
|
|
// Parameters:
|
|
// dAddr: 3bytes or 4bytes length, depend the value of mode
|
|
// data: type is char*
|
|
// len: the value is [1, FlashSize-1]
|
|
// mode: 1 means 4bytes, 0 means 3bytes
|
|
#define SEND_FASTREAD_CMD(dAddr, data, len, mode) \
|
|
{ \
|
|
SEND_MANUAL_BEGIN_CMD \
|
|
SEND_CSL_CMD \
|
|
/* write op_cmd 0x0B */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(SF_OP_FAST_RD_DATA) \
|
|
/* write address */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, ((mode)?0x04:0x03)) \
|
|
if(mode){ \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wHiWord(dAddr))) \
|
|
} \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wHiWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wLoWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wLoWord(dAddr))) \
|
|
/* write dummy data */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OS2IS, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(DUMMY_DATA) \
|
|
/* read data */ \
|
|
while((len) > 0) { \
|
|
if((len) % SF_RD_MAX) { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_INS, ((len)%SF_RD_MAX)) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} else { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_INS, SF_RD_MAX) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} \
|
|
} \
|
|
SEND_CSH_CMD \
|
|
SEND_MANUAL_END_CMD \
|
|
}
|
|
|
|
// Send fast read dual output command
|
|
// Parameters:
|
|
// dAddr: 3bytes or 4bytes length, depend the value of mode
|
|
// data: type is char*
|
|
// len: the value is [1, FlashSize-1]
|
|
// mode: 1 means 4bytes, 0 means 3bytes
|
|
#define SEND_FASTREAD_DUALOUT_CMD(dAddr, data, len, mode) \
|
|
{ \
|
|
SEND_MANUAL_BEGIN_CMD \
|
|
SEND_CSL_CMD \
|
|
/* write op_cmd 0x3B */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(SF_OP_FAST_RD_DUAL_OUT) \
|
|
/* write address */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, ((mode)?0x04:0x03)) \
|
|
if(mode){ \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wHiWord(dAddr))) \
|
|
} \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wHiWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wLoWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wLoWord(dAddr))) \
|
|
/* write dummy data */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OS2ID, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(DUMMY_DATA) \
|
|
/* read data */ \
|
|
while((len) > 0) { \
|
|
if((len) % SF_RD_MAX) { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_IND, ((len)%SF_RD_MAX)) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} else { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_IND, SF_RD_MAX) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} \
|
|
} \
|
|
SEND_CSH_CMD \
|
|
SEND_MANUAL_END_CMD \
|
|
}
|
|
|
|
// Send fast read dual I/O command
|
|
// Parameters:
|
|
// dAddr: 3bytes or 4bytes length, depend the value of mode
|
|
// data: type is char*
|
|
// len: the value is [1, FlashSize-1]
|
|
// mode: 1 means 4bytes, 0 means 3bytes
|
|
#define SEND_FASTREAD_DUALIO_CMD(dAddr, data, len, mode) \
|
|
{ \
|
|
SEND_MANUAL_BEGIN_CMD \
|
|
SEND_CSL_CMD \
|
|
/* write op_cmd 0xBB */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(SF_OP_FAST_RD_DUAL_IO) \
|
|
/* write address */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTD, ((mode)?0x04:0x03)) \
|
|
if(mode){ \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wHiWord(dAddr))) \
|
|
} \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wHiWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wLoWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wLoWord(dAddr))) \
|
|
/* write dummy data */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OD2ID, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(DUMMY_DATA) \
|
|
/* read data */ \
|
|
while((len) > 0) { \
|
|
if((len) % SF_RD_MAX) { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_IND, ((len)%SF_RD_MAX)) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} else { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_IND, SF_RD_MAX) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} \
|
|
} \
|
|
SEND_CSH_CMD \
|
|
SEND_MANUAL_END_CMD \
|
|
}
|
|
|
|
// Send page program command
|
|
// Parameters:
|
|
// dAddr: 3bytes or 4bytes length, depend the value of mode
|
|
// data: type is char*
|
|
// len: the value is [1, 256]
|
|
// mode: 1 means 4bytes, 0 means 3bytes
|
|
#define SEND_PAGE_PROGRAM_CMD(dAddr, data, len, mode) \
|
|
{ \
|
|
SEND_MANUAL_WREN_BEGIN_CMD \
|
|
SEND_CSL_CMD \
|
|
/* write op_cmd 0x02 */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(SF_OP_PAGE_PROGRAM) \
|
|
/* write address */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, ((mode)?0x04:0x03)) \
|
|
if(mode){ \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wHiWord(dAddr))) \
|
|
} \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wHiWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wLoWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wLoWord(dAddr))) \
|
|
/* page program */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, (len)) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_WRITE_CMD(*((data)++)) \
|
|
} while ((--(len)) > 0); \
|
|
SEND_CSH_CMD \
|
|
SEND_MANUAL_WREN_END_CMD \
|
|
}
|
|
|
|
// Send sector erase command
|
|
// Parameters:
|
|
// dAddr: 3bytes or 4bytes length, depend the value of mode
|
|
// mode: 1 means 4bytes, 0 means 3bytes
|
|
#define SEND_SECTOR_ERASE_CMD(dAddr, mode) \
|
|
{ \
|
|
SEND_MANUAL_WREN_BEGIN_CMD \
|
|
SEND_CSL_CMD \
|
|
/* write op_cmd 0xD8 */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(SF_OP_SECTOR_ERASE) \
|
|
/* write address */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, ((mode)?0x04:0x03)) \
|
|
if(mode){ \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wHiWord(dAddr))) \
|
|
} \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wHiWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wLoWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wLoWord(dAddr))) \
|
|
SEND_CSH_CMD \
|
|
SEND_MANUAL_WREN_END_CMD \
|
|
}
|
|
|
|
// Send bulk erase command
|
|
#define SEND_BULK_ERASE_CMD \
|
|
{ \
|
|
SEND_MANUAL_WREN_BEGIN_CMD \
|
|
send_single_opcode_cmd(SF_OP_BULK_ERASE); \
|
|
SEND_MANUAL_WREN_END_CMD \
|
|
}
|
|
|
|
// Send 4-Bytes read data command
|
|
// Parameters:
|
|
// dAddr: 4bytes length
|
|
// data: type is char*
|
|
// len: the value is [1, FlashSize-1]
|
|
#define SEND_4BYTES_READ_CMD(dAddr, data, len) \
|
|
{ \
|
|
SEND_MANUAL_BEGIN_CMD \
|
|
SEND_CSL_CMD \
|
|
/* write op_cmd 0x13 */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(SF_OP_4BYTES_RD_DATA) \
|
|
/* write address */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_THREE) \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wHiWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wHiWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wLoWord(dAddr))) \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OS2IS, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wLoWord(dAddr))) \
|
|
/* read data */ \
|
|
while((len) > 0) { \
|
|
if((len) % SF_RD_MAX) { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_INS, ((len)%SF_RD_MAX)) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} else { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_INS, SF_RD_MAX) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} \
|
|
} \
|
|
SEND_CSH_CMD \
|
|
SEND_MANUAL_END_CMD \
|
|
}
|
|
|
|
// Send 4-Bytes fast read command
|
|
// Parameters:
|
|
// dAddr: 4bytes length
|
|
// data: type is char*
|
|
// len: the value is [1, FlashSize-1]
|
|
#define SEND_4BYTES_FASTREAD_CMD(dAddr, data, len) \
|
|
{ \
|
|
SEND_MANUAL_BEGIN_CMD \
|
|
SEND_CSL_CMD \
|
|
/* write op_cmd 0x0C */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(SF_OP_4BYTES_FAST_RD_DATA) \
|
|
/* write address */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_FOUR) \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wHiWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wHiWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wLoWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wLoWord(dAddr))) \
|
|
/* write dummy data */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OS2IS, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(DUMMY_DATA) \
|
|
/* read data */ \
|
|
while((len) > 0) { \
|
|
if((len) % SF_RD_MAX) { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_INS, ((len)%SF_RD_MAX)) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} else { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_INS, SF_RD_MAX) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} \
|
|
} \
|
|
SEND_CSH_CMD \
|
|
SEND_MANUAL_END_CMD \
|
|
}
|
|
|
|
// Send 4-Bytes fast read dual output command
|
|
// Parameters:
|
|
// dAddr: 4bytes length
|
|
// data: type is char*
|
|
// len: the value is [1, FlashSize-1]
|
|
#define SEND_4BYTES_FASTREAD_DUALOUT_CMD(dAddr, data, len) \
|
|
{ \
|
|
SEND_MANUAL_BEGIN_CMD \
|
|
SEND_CSL_CMD \
|
|
/* write op_cmd 0x3C */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(SF_OP_4BYTES_FAST_RD_DUAL_OUT) \
|
|
/* write address */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_FOUR) \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wHiWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wHiWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wLoWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wLoWord(dAddr))) \
|
|
/* write dummy data */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OS2ID, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(DUMMY_DATA) \
|
|
/* read data */ \
|
|
while((len) > 0) { \
|
|
if((len) % SF_RD_MAX) { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_IND, ((len)%SF_RD_MAX)) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} else { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_IND, SF_RD_MAX) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} \
|
|
} \
|
|
SEND_CSH_CMD \
|
|
SEND_MANUAL_END_CMD \
|
|
}
|
|
|
|
// Send 4-Bytes fast read dual I/O command
|
|
// Parameters:
|
|
// dAddr: 4bytes length
|
|
// data: type is char*
|
|
// len: the value is [1, FlashSize-1]
|
|
#define SEND_4BYTES_FASTREAD_DUALIO_CMD(dAddr, data, len) \
|
|
{ \
|
|
SEND_MANUAL_BEGIN_CMD \
|
|
SEND_CSL_CMD \
|
|
/* write op_cmd 0xBC */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTS, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(SF_OP_4BYTES_FAST_RD_DUAL_IO) \
|
|
/* write address */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OUTD, OP_REPEAT_FOUR) \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wHiWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wHiWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bHiByte(wLoWord(dAddr))) \
|
|
SEND_DFIFO_WRITE_CMD(bLoByte(wLoWord(dAddr))) \
|
|
/* write dummy data */ \
|
|
SEND_OPFIFO_WRITE_CMD(OP_OD2ID, OP_REPEAT_ONE) \
|
|
SEND_DFIFO_WRITE_CMD(DUMMY_DATA) \
|
|
/* read data */ \
|
|
while((len) > 0) { \
|
|
if((len) % SF_RD_MAX) { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_IND, ((len)%SF_RD_MAX)) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} else { \
|
|
SEND_OPFIFO_WRITE_CMD(OP_IND, SF_RD_MAX) \
|
|
do \
|
|
{ \
|
|
SEND_DFIFO_READ_CMD(*((data)++)) \
|
|
} while ((--(len)) % SF_RD_MAX); \
|
|
} \
|
|
} \
|
|
SEND_CSH_CMD \
|
|
SEND_MANUAL_END_CMD \
|
|
}
|
|
|
|
// Send enter 4bytes address mode command
|
|
#define SEND_ENTER_4BYTES_MODE_CMD \
|
|
{ \
|
|
SEND_MANUAL_BEGIN_CMD \
|
|
send_single_opcode_cmd(SF_OP_ENTER_4BYTES_MODE); \
|
|
SEND_MANUAL_END_CMD \
|
|
}
|
|
|
|
// Send exit 4bytes address mode command
|
|
#define SEND_EXIT_4BYTES_MODE_CMD \
|
|
{ \
|
|
SEND_MANUAL_BEGIN_CMD \
|
|
send_single_opcode_cmd(SF_OP_EXIT_4BYTES_MODE); \
|
|
SEND_MANUAL_END_CMD \
|
|
}
|
|
|
|
// Send enter 4bytes address mode command with Write Enable
|
|
#define SEND_ENTER_4BYTES_MODE_WREN_CMD \
|
|
{ \
|
|
SEND_MANUAL_WREN_BEGIN_CMD \
|
|
send_single_opcode_cmd(SF_OP_ENTER_4BYTES_MODE); \
|
|
SEND_MANUAL_WREN_END_CMD \
|
|
}
|
|
|
|
// Send exit 4bytes address mode command with Write Enable
|
|
#define SEND_EXIT_4BYTES_MODE_WREN_CMD \
|
|
{ \
|
|
SEND_MANUAL_WREN_BEGIN_CMD \
|
|
send_single_opcode_cmd(SF_OP_EXIT_4BYTES_MODE); \
|
|
SEND_MANUAL_WREN_END_CMD \
|
|
}
|
|
|
|
|
|
// Send power down command
|
|
#define SEND_POWER_DOWN_CMD \
|
|
{ \
|
|
SEND_MANUAL_BEGIN_CMD \
|
|
send_single_opcode_cmd(SF_OP_POWER_DOWN); \
|
|
SEND_MANUAL_END_CMD \
|
|
}
|
|
|
|
// Send release power down command
|
|
#define SEND_RELEASE_POWER_DOWN_CMD \
|
|
{ \
|
|
SEND_MANUAL_BEGIN_CMD \
|
|
send_single_opcode_cmd(SF_OP_RELEASE_POWER_DOWN); \
|
|
SEND_MANUAL_END_CMD \
|
|
}
|
|
|
|
// Send read jedec id command
|
|
// Parameters:
|
|
// data: type is char[3]
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#define SEND_RD_ID_CMD(data) \
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{ \
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SEND_MANUAL_BEGIN_CMD \
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SEND_CSL_CMD \
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/* write op_cmd 0x9F */ \
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SEND_OPFIFO_WRITE_CMD(OP_OS2IS, OP_REPEAT_ONE) \
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SEND_DFIFO_WRITE_CMD(SF_OP_RD_ID) \
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/* read data */ \
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SEND_OPFIFO_WRITE_CMD(OP_INS, OP_REPEAT_THREE) \
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SEND_DFIFO_READ_CMD(*(data)) \
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SEND_DFIFO_READ_CMD(*((data)+1)) \
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SEND_DFIFO_READ_CMD(*((data)+2)) \
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SEND_CSH_CMD \
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SEND_MANUAL_END_CMD \
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}
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// change from auto mode 2 manual mode
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#define SEND_AUTO2MANUAL_CMD \
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{ \
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/* set 9 to SF_MTX_MODE_TOG */ \
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WriteReg(SF_MTX_MODE_TOG, MANUAL_MTXMODE); \
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/* enable Manual mode */ \
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WriteReg(SF_MANUAL_EN, MANUAL_MANUALEN); \
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}
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// change from manual mode 2 auto mode
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#define SEND_MANUAL2AUTO_CMD \
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{ \
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/* set 0 to SF_MTX_MODE_TOG */ \
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WriteReg(SF_MTX_MODE_TOG, AUTO_MTXMODE); \
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/* enable auto mode */ \
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WriteReg(SF_MANUAL_EN, AUTO_MANUALEN); \
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}
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// change auto mode to 3Byte address
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#define SEND_AUTO_3B_CMD \
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{ \
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/* enable auto address change */ \
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WriteReg(SF_CFG3B4B_EN, CFG3B4B_EN); \
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/* aauto address is 3Byte */ \
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WriteReg(SF_ADDR_3B4B, AUTO_3BMODE); \
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}
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// change Tn Value
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#define SEND_TN_CMD(data) \
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{ \
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/* set data to SF_SI_CK_SEL */ \
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WriteReg(SF_SI_CK_SEL, ((data) & SI_SEL_MASK)); \
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}
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// change auto mode to 4Byte address
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#define SEND_AUTO_4B_CMD \
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{ \
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/* enable auto address change */ \
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WriteReg(SF_CFG3B4B_EN, CFG3B4B_EN); \
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/* auto address is 4Byte */ \
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WriteReg(SF_ADDR_3B4B, AUTO_4BMODE); \
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}
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// Enable Auto Mode Read Idle Capability
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#define SEND_READ_IDLE_EN_CMD \
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{ \
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/* Enalbe Read IDLE */ \
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WriteReg(SF_READ_IDLE_EN, RD_IDLE_EN); \
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}
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// Disable Auto Mode Read Idle Capability
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#define SEND_READ_IDLE_DIS_CMD \
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{ \
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/* Disable Read IDLE */ \
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WriteReg(SF_READ_IDLE_EN, RD_IDLE_DIS); \
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}
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// change auto mode to Read
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#define SEND_AUTO_READ_CMD \
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{ \
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/* auto mode is Read */ \
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WriteReg(SF_READ_MODE, AUTO_READ); \
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}
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// change auto mode to Fast Read
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#define SEND_AUTO_FASTREAD_CMD \
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{ \
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/* auto mode is Fast Read */ \
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WriteReg(SF_READ_MODE, AUTO_FAST_READ); \
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}
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// change auto mode to Fast Read Dual Output
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#define SEND_AUTO_FASTREAD_DUALOUT_CMD \
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{ \
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/* auto mode is Fast Read Dual Output */ \
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WriteReg(SF_READ_MODE, AUTO_FAST_READ_DUALOUT); \
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}
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// change auto mode to Fast Read Dual IO
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#define SEND_AUTO_FASTREAD_DUALIO_CMD \
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{ \
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/* auto mode is Fast Read Dual IO */ \
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WriteReg(SF_READ_MODE, AUTO_FAST_READ_DUALIO); \
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}
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#endif
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