89 lines
2.8 KiB
Plaintext
Executable File
89 lines
2.8 KiB
Plaintext
Executable File
#
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# Memory devices
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#
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menuconfig MEMORY
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bool "Memory Controller drivers"
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if MEMORY
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config ATMEL_SDRAMC
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bool "Atmel (Multi-port DDR-)SDRAM Controller"
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default y
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depends on ARCH_AT91 && OF
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help
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This driver is for Atmel SDRAM Controller or Atmel Multi-port
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DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
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Starting with the at91sam9g45, this controller supports SDR, DDR and
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LP-DDR memories.
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config TI_AEMIF
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tristate "Texas Instruments AEMIF driver"
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depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
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help
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This driver is for the AEMIF module available in Texas Instruments
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SoCs. AEMIF stands for Asynchronous External Memory Interface and
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is intended to provide a glue-less interface to a variety of
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asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
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of 256M bytes of any of these memories can be accessed at a given
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time via four chip selects with 64M byte access per chip select.
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config TI_EMIF
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tristate "Texas Instruments EMIF driver"
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depends on ARCH_OMAP2PLUS
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select DDR
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help
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This driver is for the EMIF module available in Texas Instruments
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SoCs. EMIF is an SDRAM controller that, based on its revision,
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supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
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This driver takes care of only LPDDR2 memories presently. The
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functions of the driver includes re-configuring AC timing
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parameters and other settings during frequency, voltage and
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temperature changes
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config MVEBU_DEVBUS
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bool "Marvell EBU Device Bus Controller"
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default y
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depends on PLAT_ORION && OF
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help
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This driver is for the Device Bus controller available in some
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Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
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Armada 370 and Armada XP. This controller allows to handle flash
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devices such as NOR, NAND, SRAM, and FPGA.
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config TEGRA20_MC
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bool "Tegra20 Memory Controller(MC) driver"
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default y
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depends on ARCH_TEGRA_2x_SOC
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help
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This driver is for the Memory Controller(MC) module available
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in Tegra20 SoCs, mainly for a address translation fault
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analysis, especially for IOMMU/GART(Graphics Address
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Relocation Table) module.
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config TEGRA30_MC
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bool "Tegra30 Memory Controller(MC) driver"
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default y
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depends on ARCH_TEGRA_3x_SOC
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help
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This driver is for the Memory Controller(MC) module available
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in Tegra30 SoCs, mainly for a address translation fault
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analysis, especially for IOMMU/SMMU(System Memory Management
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Unit) module.
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config FSL_CORENET_CF
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tristate "Freescale CoreNet Error Reporting"
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depends on FSL_SOC_BOOKE
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help
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Say Y for reporting of errors from the Freescale CoreNet
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Coherency Fabric. Errors reported include accesses to
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physical addresses that mapped by no local access window
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(LAW) or an invalid LAW, as well as bad cache state that
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represents a coherency violation.
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config FSL_IFC
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bool
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depends on FSL_SOC
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endif
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