413 lines
13 KiB
C
Executable File
413 lines
13 KiB
C
Executable File
#include <asm/tc3162/tc3162.h>
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#include <linux/delay.h>
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//#define PCIE_PHY_DEBUG 1
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#define ENABLE 1
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#define DISABLE 0
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#if defined(TCSUPPORT_BONDING)
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extern unsigned long slaveVirBaseAddr;
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#endif
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#if 0 //for FPGA auto scan timing
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#define PCIe_AUTO_SCAN_TIMING 1
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#define PCIE_7510_FPGA_TIMING_PHY_P0 12
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#define PCIE_7510_FPGA_TIMING_PHY_P1 13
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#define PHY_PORT0 0
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#define PHY_PORT1 1
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static int pcie_reset_link(check_addr)
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{
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int i;
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uint32 tmp;
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//PCI-E reset
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/* enabled PCIe port 1 */
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VPint(0xbfb00088) |= (1<<22);
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mdelay(1);
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/*first reset to default*/
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VPint(0xbfb00834) &= ~((1<<26) | (1<<27) | (1<<29));
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mdelay(1);
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VPint(0xbfb00834) |= ((1<<26) | (1<<27) | (1<<29));
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mdelay(1);
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VPint(0xbfb00834) &= ~((1<<26) | (1<<27) | (1<<29));
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mdelay(1);
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//relese pcie device reset
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VPint(0xbfb80000) &= ~((1<<1) | (1<<2));
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mdelay(1);
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//start to check pcie if link up
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//wait device link up
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for(i=1 ; i<601 ; i++){
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mdelay(1);
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if((VPint(check_addr) & 0x1) != 0){
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break;
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}
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if((i%100)==0){//reset device PCIe MAC if not link up every 100ms biker_20120816
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//pcie reset again
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VPint(0xbfb80000) |= ((1<<1) | (1<<2));
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mdelay(1);
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VPint(0xbfb80000) &= ~((1<<1) | (1<<2));
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mdelay(1);
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}
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}
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if(i == 601)
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return -1;
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else
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return 0;
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}
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#endif
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void pcie_phy_force_mode_en(char enable, char rc_num){
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if(isFPGA)
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return;
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//printk("pcie_phy_force_mode_en %x %x \n",enable,rc_num);
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if(enable == ENABLE) //means disable
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{
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switch (rc_num){
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case 0:
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regWrite32(0xbfaf202c, 0x1010);
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regWrite32(0xbfaf202c, 0x1090);
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regWrite32(0xbfaf202c, 0x1010);
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break;
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case 1:
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regWrite32(0xbfaf212c, 0x1010);
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regWrite32(0xbfaf212c, 0x1090);
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regWrite32(0xbfaf212c, 0x1010);
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break;
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#if defined(TCSUPPORT_BONDING)
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case 2: //external chip use for bonding
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if(slaveVirBaseAddr != 0){
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regWrite32(slaveVirBaseAddr + 0xaf202c, 0x1010);
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regWrite32(slaveVirBaseAddr + 0xaf202c, 0x1090);
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regWrite32(slaveVirBaseAddr + 0xaf202c, 0x1010);
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regWrite32(slaveVirBaseAddr + 0xaf212c, 0x1010);
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regWrite32(slaveVirBaseAddr + 0xaf212c, 0x1090);
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regWrite32(slaveVirBaseAddr + 0xaf212c, 0x1010);
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}
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break;
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#endif
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default:
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printk("RC number %d Error !! \n",rc_num);
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break;
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}
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}
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else
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{
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switch (rc_num){
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case 0:
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regWrite32(0xbfaf202c, 0x0);
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regWrite32(0xbfaf202c, 0x80);
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regWrite32(0xbfaf202c, 0x0);
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break;
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case 1:
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regWrite32(0xbfaf212c, 0x0);
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regWrite32(0xbfaf212c, 0x80);
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regWrite32(0xbfaf212c, 0x0);
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break;
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#if defined(TCSUPPORT_BONDING)
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case 2: //external
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if(slaveVirBaseAddr != 0){
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regWrite32(slaveVirBaseAddr + 0xaf202c, 0x0);
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regWrite32(slaveVirBaseAddr + 0xaf202c, 0x80);
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regWrite32(slaveVirBaseAddr + 0xaf202c, 0x0);
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regWrite32(slaveVirBaseAddr + 0xaf212c, 0x0);
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regWrite32(slaveVirBaseAddr + 0xaf212c, 0x80);
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regWrite32(slaveVirBaseAddr + 0xaf212c, 0x0);
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}
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break;
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#endif
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default:
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printk("RC number %d Error !! \n",rc_num);
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break;
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}
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}
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}
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void init_60901(void)
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{
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uint32 tmp;
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#ifdef PCIE_PHY_DEBUG
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printk("biker1_pcie_phy_init debug message: master init \n");
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printk("debug: read address 0xbfaf24a0 (380389); value is: %lx\n",VPint(0xbfaf24a0));
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printk("debug: read address 0xbfaf24a8 (E80E8); value is: %lx\n",VPint(0xbfaf24a8));
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#endif
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//init Master
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//init 20MHz or 25MHz
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tmp = (regRead32(0xbfb0008c)&(0x3 <<22))>>22;
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if (tmp == 0x1 )
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{
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//xtal is 20MHz
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#ifdef PCIE_PHY_DEBUG
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printk("xtal is 20MHz \n");
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#endif
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//I2C 70 0xA8[11:00] 0x74 RW RG_PE1_H_LCDDS_SSC_DELTA //Improve SSC deviation
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//tmp = regRead32(0xbfaf24a8);
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regWrite32(0xbfaf24a8, 0x740074);
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//VPint(0xbfaf24a8) = (VPint(0xbfaf24a8) & (~0xfff )) | (0x74);
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mdelay(1);
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//I2C 70 0xA8[23:16] 0x74 RW RG_PE1_H_LCDDS_SSC_DELTA1 //Improve SSC deviation
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//VPint(0xbfaf24a8) = (VPint(0xbfaf24a8) & (~(0xfff <<16))) | (0x74<<16);
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//I2C 70 0xA0[19:19] 0x00 RW RG_PE1_H_LCDDS_SSC_EN //Disable SSC
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tmp = regRead32(0xbfaf24a0);
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regWrite32(0xbfaf24a0, tmp & (~(0x1 <<19)) );
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//VPint(0xbfaf24a0) = VPint(0xbfaf24a0) & (~(0x1 <<19)) ;
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mdelay(1);
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//I2C 70 0xA0[19:19] 0x01 RW RG_PE1_H_LCDDS_SSC_EN //Enable SSC
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tmp = regRead32(0xbfaf24a0);
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regWrite32(0xbfaf24a0, tmp | (0x1<<19) );
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//VPint(0xbfaf24a0) = VPint(0xbfaf24a0) | (0x1<<19);
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mdelay(1);
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}else if(tmp == 0x0 )
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{
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//xtal is 25MHz
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#ifdef PCIE_PHY_DEBUG
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printk("xtal is 25MHz \n");
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#endif
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// I2C 70 0xFC[31:24] 0x00 RW //Change bank address to 0x00
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// I2C 70 0x00[04:04] 0x01 RW rg_pe1_frc_phy_en //Force Port 0 disable control
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regWrite32(0xbfaf2000, (regRead32(0xbfaf2000) &(~(0x1 <<4)) ) | (0x1<<4) );
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mdelay(1);
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// I2C 70 0xFC[31:24] 0x01 RW //Change bank address to 0x01
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// I2C 70 0x00[04:04] 0x01 RW rg_pe1_frc_phy_en //Force Port 1 disable control
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regWrite32(0xbfaf2100, (regRead32(0xbfaf2100) &(~(0x1 <<4)) ) | (0x1<<4) );
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mdelay(1);
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// I2C 70 0xFC[31:24] 0x00 RW //Change bank address to 0x00
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// I2C 70 0x00[05:05] 0x00 RW rg_pe1_phy_en //Port 0 disable
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regWrite32(0xbfaf2000, (regRead32(0xbfaf2000) &(~(0x1 <<5)) ) );
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mdelay(1);
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// I2C 70 0xFC[31:24] 0x01 RW //Change bank address to 0x01
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// I2C 70 0x00[05:05] 0x00 RW rg_pe1_phy_en //Port 1 disable
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regWrite32(0xbfaf2100, (regRead32(0xbfaf2100) &(~(0x1 <<5)) ) );
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mdelay(1);
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// I2C 70 0xFC[31:24] 0x04 RW //Change bank address to 0x04
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// I2C 70 0x00[08:08] 0x01 RW rg_pe1_frc_h_xtal_type //
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regWrite32(0xbfaf2400, (regRead32(0xbfaf2400) &(~(0x1 <<8)) ) | (0x1<<8) );
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mdelay(1);
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// I2C 70 0x00[10:09] 0x00 RW rg_pe1_h_xtal_type //
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regWrite32(0xbfaf2400, (regRead32(0xbfaf2400) &(~(0x3 <<9)) ) );
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mdelay(1);
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// I2C 70 0x90[15:12] 0x0A RW RG_PE1_H_PLL_IR //
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regWrite32(0xbfaf2490, (regRead32(0xbfaf2490) &(~(0xf <<12)) ) | (0xA<<12) );
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mdelay(1);
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// I2C 70 0xAC[18:16] 0x01 RW RG_PE1_H_PLL_BR //
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regWrite32(0xbfaf24AC, (regRead32(0xbfaf24AC) &(~(0x7 <<16)) ) | (0x1<<16) );
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mdelay(1);
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// I2C 70 0x9C[30:16] 0x1900 RW RG_PE1_H_LCDDS_PCW_NCPO //
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regWrite32(0xbfaf249C, (regRead32(0xbfaf249C) &(~(0x7fff <<16)) ) | (0x1900<<16) );
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mdelay(1);
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// I2C 70 0x9C[31:31] 0x00 RW RG_PE1_H_LCDDS_PCW_NCPO_CHG //
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regWrite32(0xbfaf249C, (regRead32(0xbfaf249C) &(~(0x1 <<31)) ) );
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mdelay(1);
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// I2C 70 0x9C[31:31] 0x01 RW RG_PE1_H_LCDDS_PCW_NCPO_CHG //
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regWrite32(0xbfaf249C, regRead32(0xbfaf249C) | (0x1<<31) );
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mdelay(1);
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// I2C 70 0xA4[15:00] 0x018D RW RG_PE1_H_LCDDS_SSC_PRD //
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regWrite32(0xbfaf24A4, (regRead32(0xbfaf24A4) &(~(0xffff )) ) | (0x18D) );
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mdelay(1);
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// I2C 70 0xA8[11:00] 0x004A RW RG_PE1_H_LCDDS_SSC_DELTA //
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regWrite32(0xbfaf24A8, (regRead32(0xbfaf24A8) &(~(0xfff )) ) | (0x4A) );
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mdelay(1);
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// I2C 70 0xA8[27:16] 0x004A RW RG_PE1_H_LCDDS_SSC_DELTA1 //
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regWrite32(0xbfaf24A8, (regRead32(0xbfaf24A8) &(~(0xfff <<16)) ) | (0x4A<<16) );
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mdelay(1);
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// I2C 70 0x00[12:12] 0x01 RW rg_pe1_mstck_25m //value of mstck_25m when force mode enable
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regWrite32(0xbfaf2400, (regRead32(0xbfaf2400) ) | (0x1<<12) );
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mdelay(1);
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// I2C 70 0x00[11:11] 0x01 RW rg_pe1_frc_mstck_25m //force mode enable of mstck_25m
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regWrite32(0xbfaf2400, (regRead32(0xbfaf2400) ) | (0x1<<11) );
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mdelay(1);
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// I2C 70 0xFC[31:24] 0x00 RW //Change bank address to 0x00
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// I2C 70 0x00[05:05] 0x01 RW rg_pe1_phy_en //Port 0 enable
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regWrite32(0xbfaf2000, (regRead32(0xbfaf2000) |(0x1 <<5) ) );
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mdelay(1);
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// I2C 70 0xFC[31:24] 0x01 RW //Change bank address to 0x01
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// I2C 70 0x00[05:05] 0x01 RW rg_pe1_phy_en //Port 1 enable
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regWrite32(0xbfaf2100, (regRead32(0xbfaf2100) |(0x1 <<5) ));
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mdelay(1);
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// I2C 70 0xFC[31:24] 0x00 RW //Change bank address to 0x00
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// I2C 70 0x00[04:04] 0x00 RW rg_pe1_frc_phy_en //Force Port 0 disable control
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//regWrite32(0xbfaf2000, (regRead32(0xbfaf2000) &(~(0x1 <<4)) ));
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//mdelay(1);
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// I2C 70 0xFC[31:24] 0x01 RW //Change bank address to 0x01
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// I2C 70 0x00[04:04] 0x00 RW rg_pe1_frc_phy_en //Force Port 1 disable control
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//regWrite32(0xbfaf2100, (regRead32(0xbfaf2100) &(~(0x1 <<4)) ));
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//mdelay(1);
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// I2C 70 0xFC[31:24] 0x00 RW //Change bank address to 0x00
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}
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#ifdef PCIE_PHY_DEBUG
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printk("pcie_phy_init debug message:\n");
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printk("debug: read address 0xbfaf24a0 (380389); value is: %lx\n",VPint(0xbfaf24a0));
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printk("debug: read address 0xbfaf24a8 (740074); value is: %lx\n",VPint(0xbfaf24a8));
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#endif
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//init Slave
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}
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#if 0 //for FPGA auto scan timing
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uint8 pcie_60901_auto_scan(uint8 PHY_PORT, uint8 win_range, uint8 win_loop, uint32 check_addr)
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{
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uint8 win_init = 0;
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uint8 win_start = 0;
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uint8 win_len = 0;
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uint8 max_win_start = 0;
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uint8 max_win_len = 0;
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uint8 i = 0;
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uint8 timing = 0;
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printk(">>>>>Start to scan PCIe timing setting<<<<<\n");
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for (i=win_init; i<win_range; i++){
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if (PHY_PORT == PHY_PORT0)
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init_60901((uint32) (i%win_loop),0);
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else
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init_60901(0,(uint32) (i%win_loop));
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//printk("timing setting: %2d ",i);
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if (pcie_reset_link(check_addr) == 0){
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win_len++;
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if(win_len > max_win_len){
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max_win_len = win_len;
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max_win_start = win_start;
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}
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printk("Link up! \n");
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}else{
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win_len = 0;
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win_start = i + 1;
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printk("Not link \n");
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}
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}
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timing = (uint8) ((max_win_start%win_loop) + ((max_win_len%win_loop)>>1));
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printk("The pcie timing window start at : %d \n",max_win_start);
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printk("Window length is : %d \n",max_win_len);
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printk("The chosen PCIe: %d \n ",timing);
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return timing;
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}
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#endif
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void init_7505(void)
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{
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//For WCN ch14 de-sence issue, default Disable SSC, bit 28 => 1
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printk("Disable PCIe SSC\n");
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regWrite32(0xbfaf2414, (regRead32(0xbfaf2414) |(0x1 <<28) ));
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//change MSTSET from 1 to 5;
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mdelay(1);
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regWrite32(0xbfaf2498, ((regRead32(0xbfaf2498) &(~0xff) )|(0x5) ));
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//decrease PLL BW to improve jitter; by biker_20140721; add 25MHz_20140815
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mdelay(1);
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regWrite32(0xbfaf2400, ((regRead32(0xbfaf2400) &(~(0x1<<8)) )|(0x1<<8) ));
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mdelay(1);
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regWrite32(0xbfaf2400, ((regRead32(0xbfaf2400) &(~(0x3<<9)) )|(0x0<<9) ));
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mdelay(1);
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regWrite32(0xbfaf2000, ((regRead32(0xbfaf2000) &(~(0x1<<4)) )|(0x1<<4) ));
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mdelay(1);
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regWrite32(0xbfaf2000, ((regRead32(0xbfaf2000) &(~(0x1<<5)) )|(0x0<<5) ));
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mdelay(1);
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regWrite32(0xbfaf24ac, ((regRead32(0xbfaf24ac) &(~(0x7<<16)) )|(0x3<<16) ));
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mdelay(1);
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regWrite32(0xbfaf24bc, ((regRead32(0xbfaf24bc) &(~(0xff<<24)) )|(0x64<<24) ));
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mdelay(1);
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regWrite32(0xbfaf2490, ((regRead32(0xbfaf2490) &(~(0xf<<12)) )|(0xa<<12) ));
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mdelay(1);
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regWrite32(0xbfaf2490, ((regRead32(0xbfaf2490) &(~(0x3<<6)) )|(0x0<<6) ));
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mdelay(1);
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regWrite32(0xbfaf24c0, ((regRead32(0xbfaf24c0) &(~(0xffffffff<<0)) )|(0x19000000<<0) ));
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mdelay(1);
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regWrite32(0xbfaf24a4, ((regRead32(0xbfaf24a4) &(~(0xffff<<0)) )|(0x18d<<0) ));
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mdelay(1);
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regWrite32(0xbfaf24a8, ((regRead32(0xbfaf24a8) &(~(0xfff<<0)) )|(0x4a<<0) ));
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mdelay(1);
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regWrite32(0xbfaf24a8, ((regRead32(0xbfaf24a8) &(~(0xfff<<16)) )|(0x4a<<16) ));
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mdelay(1);
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regWrite32(0xbfaf2000, ((regRead32(0xbfaf2000) &(~(0x1<<5)) )|(0x1<<5) ));
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mdelay(1);
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regWrite32(0xbfaf2000, ((regRead32(0xbfaf2000) &(~(0x1<<4)) )|(0x0<<4) ));
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mdelay(1);
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/*MT7505 input crystall is 40Mhz*/
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//Fix frequence setting bug when hardware trap is 40MHz XTAL ;
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#if 0 //Already done in bootloader
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if(VPint(CR_AHB_HWCONF)&(1<<1)){
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VPint(0xbfaf2400) = (VPint(0xbfaf2400) | 0x100); /*force mode enable xtal type*/
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}
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#endif
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}
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void init_7512(void)
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{
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//LCDDS_CLK_PH_INV
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regWrite32(0xbfaf24a0, ((regRead32(0xbfaf24a0) &(~(0x1<<5)) )|(0x1<<5) ));
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mdelay(1);
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}
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int pciePhyInit(void){
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#if 0 //for FPGA auto scan timing
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#ifdef PCIe_AUTO_SCAN_TIMING
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timing_p0 = pcie_60901_auto_scan(PHY_PORT0,36,18,0xbfb83050);
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timing_p1 = pcie_60901_auto_scan(PHY_PORT1,36,18,0xbfb82050);
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#endif
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#endif
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if(isEN751221) {
|
|
|
|
if (!isFPGA) {
|
|
init_7512();
|
|
}
|
|
}
|
|
|
|
if(isMT7505) {
|
|
|
|
if (!isFPGA) {
|
|
init_7505();
|
|
}
|
|
}
|
|
|
|
if(isMT751020){
|
|
#if 0 //for FPGA auto scan timing
|
|
#ifdef PCIe_AUTO_SCAN_TIMING
|
|
timing_p0 = pcie_60901_auto_scan(PHY_PORT0,36,18,0xbfb83050);
|
|
timing_p1 = pcie_60901_auto_scan(PHY_PORT1,36,18,0xbfb82050);
|
|
#endif
|
|
#endif
|
|
init_60901();
|
|
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|