119 lines
2.8 KiB
C
Executable File
119 lines
2.8 KiB
C
Executable File
#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <asm/tc3162/tc3162.h>
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#ifdef CONFIG_MIPS_TC3262
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#define PCI_COMMAND_WINDOW 0xBFB80CF8
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#endif
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static struct resource tc3162_pci_io_resource = {
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.name = "pci IO space",
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.start = 0x1FB90000,
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.end = 0x1FB9FFFF,
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.flags = IORESOURCE_IO
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};
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static struct resource tc3162_pci_mem_resource = {
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.name = "pci memory space",
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.start = 0x1FBA0000,
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.end = 0x1FBCFFFF,
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.flags = IORESOURCE_MEM
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};
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extern struct pci_ops tc3162_pci_ops;
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struct pci_controller tc3162_controller = {
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.pci_ops = &tc3162_pci_ops,
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.io_resource = &tc3162_pci_io_resource,
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.mem_resource = &tc3162_pci_mem_resource,
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};
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static __init int tc3162_pci_init(void)
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{
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int pci_bios;
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unsigned long tmp;
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if(isRT63365 || isMT751020 || isMT7505 || isEN751221)
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return -1;
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#ifndef CONFIG_MIPS_TC3262
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pci_bios = regRead32(CR_AHB_HWCONF) & (1<<8);
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printk(KERN_INFO "tc3162: system has %sPCI BIOS\n",
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pci_bios ? "" : "no ");
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if (pci_bios == 0)
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return -1;
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#endif
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tmp = regRead32(CR_AHB_PCIC);
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regWrite32(CR_AHB_PCIC, (tmp & ~(1<<31)));
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mdelay(100);
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tmp = regRead32(CR_AHB_PCIC);
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regWrite32(CR_AHB_PCIC, (tmp | (1<<31)));
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mdelay(300);
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/* PCI memory byte swap enable */
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/*
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tmp = regRead32(CR_AHB_PCIC);
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regWrite32(CR_AHB_PCIC, (tmp | ((1<<24) | (1<<25))) );
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*/
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#ifdef CONFIG_MIPS_TC3262
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/*read pci enable bit from PCI bridge command window to check pci support.
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shnwind*/
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regWrite32(PCI_COMMAND_WINDOW, (1<<31));
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pci_bios = regRead32(PCI_COMMAND_WINDOW);
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printk(KERN_INFO "system has %sPCI BIOS\n",pci_bios ? "" : "no ");
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if (pci_bios == 0){
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return -1;
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}
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#endif
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/* Set I/O resource limits. */
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ioport_resource.end = 0x1fffffff;
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iomem_resource.end = 0xffffffff;
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if(isRT63165)
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{
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/* rt63165's PCI bridge has additional config registers
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* which can be direct-accessed, such as the first 3
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* registers shown below
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*/
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//Disable PCI IO SWAP.
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tmp = regRead32(0xbfb000ec);
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tmp &= ~(1<<9);
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regWrite32(0xbfb000ec, tmp);
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/* configure USB Host Control Register to
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do byte swaping in HW --Trey */
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regWrite32(0xbfb000a8, 0x00000060);
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mdelay(10);
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/* set space of PCI base address
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up to 256M --Trey*/
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regWrite32(0xbfb80010, 0x0fff0001);
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/* configure PCIArbitor Control Register to
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set priority scheme --Trey*/
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regWrite32(0xbfb80080, 0x00000079);
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//set base address of PCI
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regWrite32(0xbfb80cf8, 0x80000410);
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regWrite32(0xbfb80cfc, 0x00000000);
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//enable PCI's master, memory functions
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regWrite32(0xbfb80cf8, 0x80000404);
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regWrite32(0xbfb80cfc, 0xa4800016);
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//set PCI's latency-timer, cache-line-size
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regWrite32(0xbfb80cf8, 0x8000040c);
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regWrite32(0xbfb80cfc, 0x00002008);
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}
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register_pci_controller(&tc3162_controller);
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return 0;
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}
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arch_initcall(tc3162_pci_init);
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