399 lines
8.3 KiB
C
Executable File
399 lines
8.3 KiB
C
Executable File
/*
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* MIPS SPRAM support
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Copyright (C) 2007, 2008 MIPS Technologies, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/ptrace.h>
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#include <linux/stddef.h>
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#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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#include <asm/r4kcache.h>
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#include <asm/hazards.h>
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#include <linux/module.h>
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#include <asm/cpu.h>
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#ifdef CONFIG_MIPS_TC3262
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#include <asm/tc3162/tc3162.h>
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extern int __imem, __dmem;
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#endif
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static char *sram_allocp = NULL;
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static int sram_size = 0;
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static int sram_free = 0;
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static char *dspram_p = NULL;
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static int dspram_used_size = 0;
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static int dspram_max_size = 0x1000; //4K
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/*
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* These definitions are correct for the 24K/34K/74K SPRAM sample
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* implementation. The 4KS interpreted the tags differently...
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*/
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#define SPRAM_TAG0_ENABLE 0x00000080
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#define SPRAM_TAG0_PA_MASK 0xfffff000
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#define SPRAM_TAG1_SIZE_MASK 0xfffff000
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#define SPRAM_TAG_STRIDE 8
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#define ERRCTL_SPRAM (1 << 28)
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/* errctl access */
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#define read_c0_errctl(x) read_c0_ecc(x)
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#define write_c0_errctl(x) write_c0_ecc(x)
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/*
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* Different semantics to the set_c0_* function built by __BUILD_SET_C0
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*/
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static unsigned int bis_c0_errctl(unsigned int set)
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{
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unsigned int res;
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res = read_c0_errctl();
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write_c0_errctl(res | set);
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return res;
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}
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static void ispram_store_tag(unsigned int offset, unsigned int data)
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{
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unsigned int errctl;
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/* enable SPRAM tag access */
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errctl = bis_c0_errctl(ERRCTL_SPRAM);
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ehb();
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write_c0_taglo(data);
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ehb();
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cache_op(Index_Store_Tag_I, CKSEG0|offset);
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ehb();
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write_c0_errctl(errctl);
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ehb();
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}
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static unsigned int ispram_load_tag(unsigned int offset)
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{
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unsigned int data;
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unsigned int errctl;
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/* enable SPRAM tag access */
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errctl = bis_c0_errctl(ERRCTL_SPRAM);
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ehb();
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cache_op(Index_Load_Tag_I, CKSEG0 | offset);
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ehb();
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data = read_c0_taglo();
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ehb();
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write_c0_errctl(errctl);
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ehb();
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return data;
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}
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static void dspram_store_tag(unsigned int offset, unsigned int data)
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{
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unsigned int errctl;
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/* enable SPRAM tag access */
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errctl = bis_c0_errctl(ERRCTL_SPRAM);
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ehb();
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write_c0_dtaglo(data);
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ehb();
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cache_op(Index_Store_Tag_D, CKSEG0 | offset);
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ehb();
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write_c0_errctl(errctl);
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ehb();
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}
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static unsigned int dspram_load_tag(unsigned int offset)
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{
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unsigned int data;
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unsigned int errctl;
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errctl = bis_c0_errctl(ERRCTL_SPRAM);
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ehb();
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cache_op(Index_Load_Tag_D, CKSEG0 | offset);
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ehb();
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data = read_c0_dtaglo();
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ehb();
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write_c0_errctl(errctl);
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ehb();
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return data;
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}
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static void probe_spram(char *type,
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unsigned int base,
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unsigned int (*read)(unsigned int),
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void (*write)(unsigned int, unsigned int))
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{
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unsigned int firstsize = 0, lastsize = 0;
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unsigned int firstpa = 0, lastpa = 0, pa = 0;
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unsigned int offset = 0;
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unsigned int size, tag0, tag1;
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unsigned int enabled;
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int i;
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/*
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* The limit is arbitrary but avoids the loop running away if
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* the SPRAM tags are implemented differently
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*/
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for (i = 0; i < 8; i++) {
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tag0 = read(offset);
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tag1 = read(offset+SPRAM_TAG_STRIDE);
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pr_debug("DBG %s%d: tag0=%08x tag1=%08x\n",
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type, i, tag0, tag1);
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size = tag1 & SPRAM_TAG1_SIZE_MASK;
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if (size == 0)
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break;
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if (i != 0) {
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/* tags may repeat... */
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if ((pa == firstpa && size == firstsize) ||
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(pa == lastpa && size == lastsize))
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break;
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}
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/* Align base with size */
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base = (base + size - 1) & ~(size-1);
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/* reprogram the base address base address and enable */
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tag0 = (base & SPRAM_TAG0_PA_MASK) | SPRAM_TAG0_ENABLE;
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write(offset, tag0);
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base += size;
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/* reread the tag */
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tag0 = read(offset);
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pa = tag0 & SPRAM_TAG0_PA_MASK;
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enabled = tag0 & SPRAM_TAG0_ENABLE;
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if (i == 0) {
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firstpa = pa;
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firstsize = size;
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}
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lastpa = pa;
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lastsize = size;
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if (strcmp(type, "DSPRAM") == 0) {
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unsigned int *vp = (unsigned int *)(CKSEG1 | pa);
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unsigned int v;
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if(!isMT751020 && !isMT7505 && !isEN751221){
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#define TDAT 0x5a5aa5a5
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vp[0] = TDAT;
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vp[1] = ~TDAT;
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mb();
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v = vp[0];
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if (v != TDAT)
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printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
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vp, TDAT, v);
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v = vp[1];
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if (v != ~TDAT)
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printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
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vp+1, ~TDAT, v);
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}
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#ifdef CONFIG_MIPS_TC3262
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if (enabled) {
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if(isMT751020 || isMT7505 || isEN751221){
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dspram_max_size = size;
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}
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else{
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sram_allocp = (char *) vp;
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sram_size = sram_free = size;
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}
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}
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#endif
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}
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pr_info("%s%d: PA=%08x,Size=%08x%s\n",
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type, i, pa, size, enabled ? ",enabled" : "");
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offset += 2 * SPRAM_TAG_STRIDE;
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}
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}
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/*****************************************************************************/
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int is_sram_addr(void *p)
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{
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if ((CKSEG1ADDR(p) & 0xffffc000) == (CKSEG1ADDR(DSPRAM_BASE) & 0xffffc000))
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return 1;
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else
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return 0;
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}
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EXPORT_SYMBOL(is_sram_addr);
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void *alloc_sram(int n)
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{
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if (sram_allocp == NULL)
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return NULL;
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if (sram_free >= n) {
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sram_free -= n;
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sram_allocp += n;
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printk("alloc_sram p=%p free=%04x\n", sram_allocp, sram_free);
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return sram_allocp - n;
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} else
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return NULL;
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}
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EXPORT_SYMBOL(alloc_sram);
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void free_sram(void *p, int n)
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{
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if (sram_allocp == (p+n)) {
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sram_free += n;
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sram_allocp -= n;
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}
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printk("free_sram p=%p free=%04x\n", sram_allocp, sram_free);
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}
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EXPORT_SYMBOL(free_sram);
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void write_to_dspram(long data)
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{
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if(dspram_p == NULL || dspram_max_size == 0)
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return;
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*(long *)dspram_p = data;
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dspram_p += sizeof(long);
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dspram_used_size += sizeof(long);
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if(dspram_used_size >= dspram_max_size){
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dspram_p = (char *)(DSPRAM_BASE);
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dspram_used_size = 0;
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}
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}
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unsigned int dspram_base_addr(void)
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{
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return DSPRAM_BASE;
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}
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#define MIPS34K_Index_Store_Data_I 0x0c
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static void ispram_store_data(unsigned int offset, unsigned int datalo, unsigned int datahi)
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{
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unsigned int errctl;
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/* enable SPRAM tag access */
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errctl = bis_c0_errctl(ERRCTL_SPRAM);
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ehb();
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#ifdef CONFIG_CPU_BIG_ENDIAN
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write_c0_idatalo(datahi);
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ehb();
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write_c0_idatahi(datalo);
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ehb();
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#else
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write_c0_idatalo(datalo);
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ehb();
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write_c0_idatahi(datahi);
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ehb();
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#endif
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cache_op(MIPS34K_Index_Store_Data_I, CKSEG0|offset);
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ehb();
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write_c0_errctl(errctl);
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ehb();
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}
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void ispram_fill(void)
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{
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unsigned int pa, size, tag0, tag1;
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unsigned int offset;
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unsigned int datalo, datahi;
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tag0 = ispram_load_tag(0);
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tag1 = ispram_load_tag(0+SPRAM_TAG_STRIDE);
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pa = tag0 & SPRAM_TAG0_PA_MASK;
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size = tag1 & SPRAM_TAG1_SIZE_MASK;
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if (size == 0)
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return;
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for (offset = 0; offset < size; offset += 8) {
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datalo = *(unsigned int *) (PHYS_TO_K0(pa + offset));
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datahi = *(unsigned int *) (PHYS_TO_K0(pa + offset + 4));
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ispram_store_data(offset, datalo, datahi);
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}
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}
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void ispram_refill(void)
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{
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/*
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* probe_spram("ISPRAM", CPHYSADDR(&__imem), &ispram_load_tag, &ispram_store_tag);
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*/
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ispram_fill();
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}
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static inline void ecnt_spram_config(unsigned int config0)
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{
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#ifdef CONFIG_TC3162_IMEM
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if (config0 & (1<<24)) {
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probe_spram("ISPRAM", CPHYSADDR(&__imem),
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&ispram_load_tag, &ispram_store_tag);
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ispram_fill();
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if (!isRT63165 && !isRT63365 && !isMT751020 && !isMT7505 && !isEN751221)
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VPint(CR_DMC_ISPCFGR) = (CPHYSADDR(&__imem) & 0xfffff000) | (1<<8) | (0x7);
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}
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#endif
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#ifdef CONFIG_TC3162_DMEM
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if (config0 & (1<<23)) {
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if(isMT751020){
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probe_spram("DSPRAM", CPHYSADDR(DSPRAM_BASE),
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&dspram_load_tag, &dspram_store_tag);
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dspram_p = (char *)(DSPRAM_BASE);
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}
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else{
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probe_spram("DSPRAM", CPHYSADDR(DSPRAM_BASE),
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&dspram_load_tag, &dspram_store_tag);
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VPint(CR_DMC_DSPCFGR) = (CPHYSADDR(DSPRAM_BASE) & 0xfffff000) | (1<<8) | (0x7);
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}
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}
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#endif
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}
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/*****************************************************************************/
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void spram_config(void)
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{
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unsigned int config0;
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switch (current_cpu_type()) {
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case CPU_24K:
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case CPU_34K:
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case CPU_74K:
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case CPU_1004K:
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case CPU_1074K:
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case CPU_INTERAPTIV:
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case CPU_PROAPTIV:
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case CPU_P5600:
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config0 = read_c0_config();
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/* FIXME: addresses are Malta specific */
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#ifdef CONFIG_MIPS_TC3262
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ecnt_spram_config(config0);
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#else
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if (config0 & (1<<24)) {
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probe_spram("ISPRAM", 0x1c000000,
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&ispram_load_tag, &ispram_store_tag);
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}
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if (config0 & (1<<23))
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probe_spram("DSPRAM", 0x1c100000,
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&dspram_load_tag, &dspram_store_tag);
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#endif
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}
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}
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