526 lines
13 KiB
C
Executable File
526 lines
13 KiB
C
Executable File
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/*
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* Interrupt service routines for Trendchip board
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mipsregs.h>
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#include <asm/tc3162/tc3162.h>
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#include <linux/sched.h>
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#include <asm/setup.h>
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#ifdef CONFIG_MIPS_TC3262
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/kernel_stat.h>
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#include <linux/kernel.h>
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#include <linux/random.h>
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#include <asm/mipsmtregs.h>
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#else
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#include <linux/io.h>
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#include <asm/irq_cpu.h>
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#endif
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#define ALLINTS (IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
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#ifdef CONFIG_MIPS_TC3262
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static DEFINE_SPINLOCK(tc3162_irq_lock);
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//static inline void unmask_mips_mt_irq(unsigned int irq)
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static inline void unmask_mips_mt_irq(struct irq_data *d)
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{
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unsigned int irq = d->irq;
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unsigned int vpflags = dvpe();
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int cpu_irq = 0;
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if ((irq == SI_SWINT1_INT1) || (irq == SI_SWINT_INT1))
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cpu_irq = 1;
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set_c0_status(0x100 << cpu_irq);
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irq_enable_hazard();
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evpe(vpflags);
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}
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//static inline void mask_mips_mt_irq(unsigned int irq)
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static inline void mask_mips_mt_irq(struct irq_data *d)
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{
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unsigned int irq = d->irq;
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unsigned int vpflags = dvpe();
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int cpu_irq = 0;
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if ((irq == SI_SWINT1_INT1) || (irq == SI_SWINT_INT1))
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cpu_irq = 1;
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clear_c0_status(0x100 << cpu_irq);
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irq_disable_hazard();
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evpe(vpflags);
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}
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//static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
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static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
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{
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unsigned int irq = d->irq;
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unsigned int vpflags = dvpe();
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unsigned long int tmp;
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int cpu_irq = 0;
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if ((irq == SI_SWINT1_INT1) || (irq == SI_SWINT_INT1))
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cpu_irq = 1;
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#ifdef TCSUPPORT_MT7510_E1
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READ_E1(CR_INTC_IMR);
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#endif
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tmp = regRead32(CR_INTC_IMR);
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tmp |= (1 << (irq-1));
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if (irq == SI_SWINT_INT0){
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tmp |= (1 << (SI_SWINT1_INT0-1));
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}else if (irq == SI_SWINT_INT1){
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tmp |= (1 << (SI_SWINT1_INT1-1));
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}
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regWrite32(CR_INTC_IMR, tmp);
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clear_c0_cause(0x100 << cpu_irq);
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evpe(vpflags);
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unmask_mips_mt_irq(d);
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return 0;
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}
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/*
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* While we ack the interrupt interrupts are disabled and thus we don't need
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* to deal with concurrency issues. Same for mips_cpu_irq_end.
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*/
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//static void mips_mt_cpu_irq_ack(unsigned int irq)
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static void mips_mt_cpu_irq_ack(struct irq_data *d)
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{
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unsigned int irq = d->irq;
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unsigned int vpflags = dvpe();
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int cpu_irq = 0;
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if ((irq == SI_SWINT1_INT1) || (irq == SI_SWINT_INT1))
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cpu_irq = 1;
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clear_c0_cause(0x100 << cpu_irq);
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evpe(vpflags);
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mask_mips_mt_irq(d);
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}
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static struct irq_chip mips_mt_cpu_irq_controller = {
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.name = "MIPS",
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.irq_startup = mips_mt_cpu_irq_startup,
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.irq_ack = mips_mt_cpu_irq_ack,
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.irq_mask = mask_mips_mt_irq,
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.irq_mask_ack = mips_mt_cpu_irq_ack,
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.irq_unmask = unmask_mips_mt_irq,
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.irq_eoi = unmask_mips_mt_irq,
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};
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#define __BUILD_IRQ_DISPATCH(irq_n) \
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static void __tc3262_irq_dispatch##irq_n(void) \
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{ \
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do_IRQ(irq_n); \
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}
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#define __BUILD_IRQ_DISPATCH_FUNC(irq_n) __tc3262_irq_dispatch##irq_n
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/* pre-built 64 irq dispatch function */
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__BUILD_IRQ_DISPATCH(0)
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__BUILD_IRQ_DISPATCH(1)
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__BUILD_IRQ_DISPATCH(2)
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__BUILD_IRQ_DISPATCH(3)
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__BUILD_IRQ_DISPATCH(4)
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__BUILD_IRQ_DISPATCH(5)
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__BUILD_IRQ_DISPATCH(6)
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__BUILD_IRQ_DISPATCH(7)
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__BUILD_IRQ_DISPATCH(8)
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__BUILD_IRQ_DISPATCH(9)
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__BUILD_IRQ_DISPATCH(10)
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__BUILD_IRQ_DISPATCH(11)
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__BUILD_IRQ_DISPATCH(12)
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__BUILD_IRQ_DISPATCH(13)
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__BUILD_IRQ_DISPATCH(14)
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__BUILD_IRQ_DISPATCH(15)
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__BUILD_IRQ_DISPATCH(16)
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__BUILD_IRQ_DISPATCH(17)
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__BUILD_IRQ_DISPATCH(18)
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__BUILD_IRQ_DISPATCH(19)
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__BUILD_IRQ_DISPATCH(20)
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__BUILD_IRQ_DISPATCH(21)
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__BUILD_IRQ_DISPATCH(22)
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__BUILD_IRQ_DISPATCH(23)
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__BUILD_IRQ_DISPATCH(24)
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__BUILD_IRQ_DISPATCH(25)
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__BUILD_IRQ_DISPATCH(26)
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__BUILD_IRQ_DISPATCH(27)
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__BUILD_IRQ_DISPATCH(28)
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__BUILD_IRQ_DISPATCH(29)
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__BUILD_IRQ_DISPATCH(30)
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__BUILD_IRQ_DISPATCH(31)
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__BUILD_IRQ_DISPATCH(32)
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__BUILD_IRQ_DISPATCH(33)
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__BUILD_IRQ_DISPATCH(34)
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__BUILD_IRQ_DISPATCH(35)
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__BUILD_IRQ_DISPATCH(36)
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__BUILD_IRQ_DISPATCH(37)
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__BUILD_IRQ_DISPATCH(38)
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__BUILD_IRQ_DISPATCH(39)
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__BUILD_IRQ_DISPATCH(40)
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__BUILD_IRQ_DISPATCH(41)
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__BUILD_IRQ_DISPATCH(42)
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__BUILD_IRQ_DISPATCH(43)
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__BUILD_IRQ_DISPATCH(44)
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__BUILD_IRQ_DISPATCH(45)
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__BUILD_IRQ_DISPATCH(46)
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__BUILD_IRQ_DISPATCH(47)
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__BUILD_IRQ_DISPATCH(48)
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__BUILD_IRQ_DISPATCH(49)
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__BUILD_IRQ_DISPATCH(50)
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__BUILD_IRQ_DISPATCH(51)
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__BUILD_IRQ_DISPATCH(52)
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__BUILD_IRQ_DISPATCH(53)
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__BUILD_IRQ_DISPATCH(54)
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__BUILD_IRQ_DISPATCH(55)
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__BUILD_IRQ_DISPATCH(56)
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__BUILD_IRQ_DISPATCH(57)
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__BUILD_IRQ_DISPATCH(58)
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__BUILD_IRQ_DISPATCH(59)
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__BUILD_IRQ_DISPATCH(60)
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__BUILD_IRQ_DISPATCH(61)
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__BUILD_IRQ_DISPATCH(62)
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__BUILD_IRQ_DISPATCH(63)
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/* register pre-built 64 irq dispatch function */
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static void (*irq_dispatch_tab[])(void) =
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{
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__BUILD_IRQ_DISPATCH_FUNC(0),
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__BUILD_IRQ_DISPATCH_FUNC(1),
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__BUILD_IRQ_DISPATCH_FUNC(2),
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__BUILD_IRQ_DISPATCH_FUNC(3),
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__BUILD_IRQ_DISPATCH_FUNC(4),
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__BUILD_IRQ_DISPATCH_FUNC(5),
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__BUILD_IRQ_DISPATCH_FUNC(6),
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__BUILD_IRQ_DISPATCH_FUNC(7),
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__BUILD_IRQ_DISPATCH_FUNC(8),
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__BUILD_IRQ_DISPATCH_FUNC(9),
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__BUILD_IRQ_DISPATCH_FUNC(10),
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__BUILD_IRQ_DISPATCH_FUNC(11),
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__BUILD_IRQ_DISPATCH_FUNC(12),
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__BUILD_IRQ_DISPATCH_FUNC(13),
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__BUILD_IRQ_DISPATCH_FUNC(14),
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__BUILD_IRQ_DISPATCH_FUNC(15),
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__BUILD_IRQ_DISPATCH_FUNC(16),
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__BUILD_IRQ_DISPATCH_FUNC(17),
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__BUILD_IRQ_DISPATCH_FUNC(18),
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__BUILD_IRQ_DISPATCH_FUNC(19),
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__BUILD_IRQ_DISPATCH_FUNC(20),
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__BUILD_IRQ_DISPATCH_FUNC(21),
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__BUILD_IRQ_DISPATCH_FUNC(22),
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__BUILD_IRQ_DISPATCH_FUNC(23),
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__BUILD_IRQ_DISPATCH_FUNC(24),
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__BUILD_IRQ_DISPATCH_FUNC(25),
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__BUILD_IRQ_DISPATCH_FUNC(26),
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__BUILD_IRQ_DISPATCH_FUNC(27),
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__BUILD_IRQ_DISPATCH_FUNC(28),
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__BUILD_IRQ_DISPATCH_FUNC(29),
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__BUILD_IRQ_DISPATCH_FUNC(30),
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__BUILD_IRQ_DISPATCH_FUNC(31),
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__BUILD_IRQ_DISPATCH_FUNC(32),
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__BUILD_IRQ_DISPATCH_FUNC(33),
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__BUILD_IRQ_DISPATCH_FUNC(34),
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__BUILD_IRQ_DISPATCH_FUNC(35),
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__BUILD_IRQ_DISPATCH_FUNC(36),
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__BUILD_IRQ_DISPATCH_FUNC(37),
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__BUILD_IRQ_DISPATCH_FUNC(38),
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__BUILD_IRQ_DISPATCH_FUNC(39),
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__BUILD_IRQ_DISPATCH_FUNC(40),
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__BUILD_IRQ_DISPATCH_FUNC(41),
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__BUILD_IRQ_DISPATCH_FUNC(42),
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__BUILD_IRQ_DISPATCH_FUNC(43),
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__BUILD_IRQ_DISPATCH_FUNC(44),
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__BUILD_IRQ_DISPATCH_FUNC(45),
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__BUILD_IRQ_DISPATCH_FUNC(46),
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__BUILD_IRQ_DISPATCH_FUNC(47),
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__BUILD_IRQ_DISPATCH_FUNC(48),
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__BUILD_IRQ_DISPATCH_FUNC(49),
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__BUILD_IRQ_DISPATCH_FUNC(50),
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__BUILD_IRQ_DISPATCH_FUNC(51),
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__BUILD_IRQ_DISPATCH_FUNC(52),
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__BUILD_IRQ_DISPATCH_FUNC(53),
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__BUILD_IRQ_DISPATCH_FUNC(54),
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__BUILD_IRQ_DISPATCH_FUNC(55),
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__BUILD_IRQ_DISPATCH_FUNC(56),
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__BUILD_IRQ_DISPATCH_FUNC(57),
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__BUILD_IRQ_DISPATCH_FUNC(58),
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__BUILD_IRQ_DISPATCH_FUNC(59),
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__BUILD_IRQ_DISPATCH_FUNC(60),
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__BUILD_IRQ_DISPATCH_FUNC(61),
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__BUILD_IRQ_DISPATCH_FUNC(62),
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__BUILD_IRQ_DISPATCH_FUNC(63)
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};
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#endif
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//__IMEM static inline void unmask_mips_irq(unsigned int irq)
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__IMEM static inline void unmask_mips_irq(struct irq_data *data)
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{
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//pr_info("\nUNMASK_mips_irq");
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unsigned int irq = data->irq;
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#ifdef CONFIG_MIPS_TC3262
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unsigned long flags;
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unsigned long int tmp;
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int cpu = smp_processor_id();
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//printk("unmask_mips_irq: 1! irq is %d, \r\n", irq);
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spin_lock_irqsave(&tc3162_irq_lock, flags);
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#ifdef CONFIG_MIPS_MT_SMTC
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if (cpu_data[cpu].vpe_id != 0) {
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#else
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if (cpu != 0) {
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#endif
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if (irq == SI_TIMER_INT)
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irq = SI_TIMER1_INT;
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}
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//printk("unmask_mips_irq: 2! irq is %d, \r\n", irq);
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if (irq <= 32)
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{
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#ifdef TCSUPPORT_MT7510_E1
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READ_E1(CR_INTC_IMR);
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#endif
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tmp = regRead32(CR_INTC_IMR);
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tmp |= (1 << (irq-1));
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regWrite32(CR_INTC_IMR, tmp);
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//printk("unmask_mips_irq: entered! irq is %d, CR_INTC_IMR %08x write value is [%08x]\r\n", irq, CR_INTC_IMR, tmp);
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//tmp = regRead32(CR_INTC_IMR);
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//printk("unmask_mips_irq: entered! irq is %d, REREAD CR_INTC_IMR %08x write value is [%08x]\r\n", irq, CR_INTC_IMR, tmp);
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}else
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{
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#ifdef TCSUPPORT_MT7510_E1
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READ_E1(CR_INTC_IMR_1);
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#endif
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tmp = regRead32(CR_INTC_IMR_1);
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tmp |= (1 << (irq-33));
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regWrite32(CR_INTC_IMR_1, tmp);
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//printk("unmask_mips_irq: entered! irq is %d, CR_INTC_IMR_1 %08x write value is [%08x]\r\n", irq, CR_INTC_IMR_1, tmp);
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//tmp = regRead32(CR_INTC_IMR_1);
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//printk("unmask_mips_irq: entered! irq is %d, REREAD CR_INTC_IMR_1 %08x write value is [%08x]\r\n", irq, CR_INTC_IMR_1, tmp);
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}
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spin_unlock_irqrestore(&tc3162_irq_lock, flags);
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#else
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VPint(CR_INTC_IMR) |= (1 << irq);
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#endif
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}
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//__IMEM static inline void mask_mips_irq(unsigned int irq)
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__IMEM static inline void mask_mips_irq(struct irq_data *data)
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{
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unsigned int irq = data->irq;
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#ifdef CONFIG_MIPS_TC3262
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unsigned long flags;
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unsigned long int tmp;
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int cpu = smp_processor_id();
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//printk("mask_mips_irq: 1! irq is %d, \r\n", irq);
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spin_lock_irqsave(&tc3162_irq_lock, flags);
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#ifdef CONFIG_MIPS_MT_SMTC
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if (cpu_data[cpu].vpe_id != 0) {
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#else
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if (cpu != 0) {
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#endif
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if (irq == SI_TIMER_INT)
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irq = SI_TIMER1_INT;
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}
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//printk("mask_mips_irq: 2! irq is %d, \r\n", irq);
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if (irq <= 32){
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#ifdef TCSUPPORT_MT7510_E1
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READ_E1(CR_INTC_IMR);
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#endif
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tmp = regRead32(CR_INTC_IMR);
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tmp &= ~(1 << (irq-1));
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regWrite32(CR_INTC_IMR, tmp);
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//printk("mask_mips_irq: entered! irq is %d, CR_INTC_IMR %08x write value is [%08x]\r\n", irq, CR_INTC_IMR, tmp);
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//tmp = regRead32(CR_INTC_IMR);
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//printk("mask_mips_irq: entered! irq is %d, REREAD CR_INTC_IMR %08x write value is [%08x]\r\n", irq, CR_INTC_IMR, tmp);
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}else{
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#ifdef TCSUPPORT_MT7510_E1
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READ_E1(CR_INTC_IMR_1);
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#endif
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tmp = regRead32(CR_INTC_IMR_1);
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tmp &= ~(1 << (irq-33));
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regWrite32(CR_INTC_IMR_1, tmp);
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//printk("mask_mips_irq: entered! irq is %d, CR_INTC_IMR_1 %08x write value is [%08x]\r\n", irq, CR_INTC_IMR_1, tmp);
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//tmp = regRead32(CR_INTC_IMR_1);
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//printk("mask_mips_irq: entered! irq is %d, REREAD CR_INTC_IMR_1 %08x write value is [%08x]\r\n", irq, CR_INTC_IMR_1, tmp);
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}
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spin_unlock_irqrestore(&tc3162_irq_lock, flags);
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#else
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VPint(CR_INTC_IMR) &= ~(1 << irq);
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#endif
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}
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void tc3162_enable_irq(unsigned int irq)
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{
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#ifdef CONFIG_MIPS_TC3262
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unsigned long flags;
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unsigned long int tmp;
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spin_lock_irqsave(&tc3162_irq_lock, flags);
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if (irq <= 32){
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#ifdef TCSUPPORT_MT7510_E1
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READ_E1(CR_INTC_IMR);
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#endif
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tmp = regRead32(CR_INTC_IMR);
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tmp |= (1 << (irq-1));
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regWrite32(CR_INTC_IMR, tmp);
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}else{
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#ifdef TCSUPPORT_MT7510_E1
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READ_E1(CR_INTC_IMR_1);
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#endif
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tmp = regRead32(CR_INTC_IMR_1);
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tmp |= (1 << (irq-33));
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regWrite32(CR_INTC_IMR_1, tmp);
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}
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spin_unlock_irqrestore(&tc3162_irq_lock, flags);
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#else
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VPint(CR_INTC_IMR) |= (1 << irq);
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#endif
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}
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EXPORT_SYMBOL(tc3162_enable_irq);
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void tc3162_disable_irq(unsigned int irq)
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{
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#ifdef CONFIG_MIPS_TC3262
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unsigned long flags;
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unsigned long int tmp;
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spin_lock_irqsave(&tc3162_irq_lock, flags);
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if (irq <= 32){
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#ifdef TCSUPPORT_MT7510_E1
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READ_E1(CR_INTC_IMR);
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#endif
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tmp = regRead32(CR_INTC_IMR);
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tmp &= ~(1 << (irq-1));
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regWrite32(CR_INTC_IMR, tmp);
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}else{
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#ifdef TCSUPPORT_MT7510_E1
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READ_E1(CR_INTC_IMR_1);
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#endif
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tmp = regRead32(CR_INTC_IMR_1);
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tmp &= ~(1 << (irq-33));
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regWrite32(CR_INTC_IMR_1, tmp);
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}
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spin_unlock_irqrestore(&tc3162_irq_lock, flags);
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#else
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VPint(CR_INTC_IMR) &= ~(1 << (irq-1));
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#endif
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}
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EXPORT_SYMBOL(tc3162_disable_irq);
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#ifdef CONFIG_MIPS_MT_SMP
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extern int plat_set_irq_affinity(unsigned int irq,
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const struct cpumask *affinity);
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#endif
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static struct irq_chip tc3162_irq_chip = {
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.name = "MIPS",
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.irq_ack = mask_mips_irq,
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.irq_mask = mask_mips_irq,
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.irq_mask_ack = mask_mips_irq,
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.irq_unmask = unmask_mips_irq,
|
|
.irq_eoi = unmask_mips_irq,
|
|
#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
|
|
.irq_set_affinity = plat_set_irq_affinity,
|
|
#else
|
|
#ifdef CONFIG_MIPS_MT_SMP
|
|
.irq_set_affinity = plat_set_irq_affinity,
|
|
#endif
|
|
#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
|
|
};
|
|
|
|
extern void vsmp_int_init(void);
|
|
|
|
void __init arch_init_irq(void)
|
|
{
|
|
unsigned int i;
|
|
|
|
/* Disable all hardware interrupts */
|
|
clear_c0_status(ST0_IM);
|
|
clear_c0_cause(CAUSEF_IP);
|
|
|
|
/* Initialize IRQ action handlers */
|
|
for (i = 0; i < NR_IRQS; i++) {
|
|
#ifdef CONFIG_MIPS_TC3262
|
|
/*
|
|
* Only MT is using the software interrupts currently, so we just
|
|
* leave them uninitialized for other processors.
|
|
*/
|
|
if (cpu_has_mipsmt) {
|
|
if ((i == SI_SWINT1_INT0) || (i == SI_SWINT1_INT1) ||
|
|
(i == SI_SWINT_INT0) || (i == SI_SWINT_INT1)) {
|
|
irq_set_chip(i, &mips_mt_cpu_irq_controller);
|
|
continue;
|
|
}
|
|
}
|
|
|
|
if ((i == SI_TIMER_INT) || (i == SI_TIMER1_INT))
|
|
irq_set_chip_and_handler(i, &tc3162_irq_chip,
|
|
handle_percpu_irq);
|
|
else
|
|
irq_set_chip_and_handler(i, &tc3162_irq_chip,
|
|
handle_level_irq);
|
|
#else
|
|
irq_set_chip_and_handler(i, &tc3162_irq_chip,
|
|
handle_level_irq);
|
|
#endif
|
|
}
|
|
|
|
#ifdef CONFIG_MIPS_TC3262
|
|
if (cpu_has_veic || cpu_has_vint) {
|
|
write_c0_status((read_c0_status() & ~ST0_IM ) |
|
|
(STATUSF_IP0 | STATUSF_IP1));
|
|
|
|
/* register irq dispatch functions */
|
|
for (i = 0; i < NR_IRQS; i++)
|
|
set_vi_handler(i, irq_dispatch_tab[i]);
|
|
} else {
|
|
change_c0_status(ST0_IM, ALLINTS);
|
|
}
|
|
#else
|
|
/* Enable all interrupts */
|
|
change_c0_status(ST0_IM, ALLINTS);
|
|
#endif
|
|
#ifdef CONFIG_MIPS_MT_SMP
|
|
vsmp_int_init();
|
|
#endif
|
|
}
|
|
|
|
__IMEM asmlinkage void plat_irq_dispatch(void)
|
|
{
|
|
#ifdef CONFIG_MIPS_TC3262
|
|
int irq = ((read_c0_cause() & ST0_IM) >> 10);
|
|
pr_info("\nplat_irq_dispatch, irq = %d", irq);
|
|
do_IRQ(irq);
|
|
#else
|
|
do_IRQ(VPint(CR_INTC_IVR));
|
|
#endif
|
|
}
|
|
|