688 lines
15 KiB
C
Executable File
688 lines
15 KiB
C
Executable File
#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/random.h>
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#include <asm/bitops.h>
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#include <asm/bootinfo.h>
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#include <asm/irq.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <linux/circ_buf.h>
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#include <asm/tc3162.h>
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#include <asm/io.h>
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#include "skbuff.h"
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#include "eth.h"
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#include "tc3162l2mac.h"
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#define printf prom_printf
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static macAdapter_t DummyAdapter;
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macAdapter_t *mac_p = &DummyAdapter;
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static macMemPool_t enetMemPool __attribute__ ((__aligned__(16)));
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#define read_reg_word(reg) VPint(reg);
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#define write_reg_word(reg, wdata) VPint(reg)=wdata;
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extern void pause(int ms);
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PUBLIC void
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miiStationWrite(
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uint32 enetPhyAddr,
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uint32 phyReg,
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uint32 miiData
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)
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{
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uint32 cnt=1000;
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uint32 reg=0;
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macPhyWDataReg_t macPHYWData;
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macPHYWData.bits.miiwdata = miiData & 0x0000ffff;
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write_reg_word (CR_MAC_PHYWDATA, macPHYWData.value);
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if(isTC3162U || isRT63260){
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/*New format to access mii register*/
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reg=((phyReg & 0x1f)<<NEW_PHYOR_REG_SHIFT) |((enetPhyAddr & 0x1f) <<NEW_PHYOR_ADDR_SHIFT)\
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|(NEW_PHYOR_OP_WR<<NEW_PHYOR_OP_SHIFT) |(NEW_PHYOR_ST_IEEE_OLD <<NEW_PHYOR_ST_SHIFT);
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write_reg_word (CR_MAC_PHYCR, reg);
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do{
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reg=read_reg_word (CR_MAC_PHYCR);
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cnt--;
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}while ((reg&NEW_PHYOR_BUSY)&&cnt>0);
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}
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else{
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/*Old format to accress mii register*/
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reg=((phyReg & 0x1f)<<PHYOR_REG_SHIFT) |((enetPhyAddr & 0x1f) <<PHYOR_ADDR_SHIFT) \
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|PHYOR_WRITE;
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write_reg_word (CR_MAC_PHYCR, reg);
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do{
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reg=read_reg_word (CR_MAC_PHYCR);
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cnt--;
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}while ((reg & PHYOR_WRITE)&&cnt>0);
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}
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if(cnt==0){
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printf("Error:miiStationWrite Timeout!");
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}
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}
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PUBLIC uint32
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miiStationRead(
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uint32 enetPhyAddr,
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uint32 phyReg
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)
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{
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uint32 reg=0;
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uint32 cnt=1000;
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if(isTC3162U || isRT63260){
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/*New format to access mii register*/
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reg=((phyReg & 0x1f)<<NEW_PHYOR_REG_SHIFT) |((enetPhyAddr & 0x1f) <<NEW_PHYOR_ADDR_SHIFT)\
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|(NEW_PHYOR_OP_RD<<NEW_PHYOR_OP_SHIFT) |(NEW_PHYOR_ST_IEEE_OLD <<NEW_PHYOR_ST_SHIFT);
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write_reg_word (CR_MAC_PHYCR, reg);
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do{
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reg=read_reg_word (CR_MAC_PHYCR);
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cnt--;
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}while ((reg&NEW_PHYOR_BUSY)&&cnt>0);
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}
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else{
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/*Old format to accress mii register*/
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reg=((phyReg & 0x1f)<<PHYOR_REG_SHIFT) |((enetPhyAddr & 0x1f) <<PHYOR_ADDR_SHIFT) \
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|PHYOR_READ;
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write_reg_word (CR_MAC_PHYCR, reg);
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do{
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reg=read_reg_word (CR_MAC_PHYCR);
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cnt--;
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}while ((reg&PHYOR_READ)&&cnt>0);
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}
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if(cnt==0){
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printf("Error:miiStationRead Timeout!");
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}
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return (reg & 0xffff);
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}
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void macResetSwMAC(void)
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{
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macCtrlReg_t macCtrl;
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// Disable DMA Enable
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macCtrl.value = 0;
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write_reg_word (CR_MAC_MACCR, macCtrl.value);
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pause(2);
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// Reset Mac
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// macCtrl.value = 0;
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macCtrl.bits.sw_rst = 1;
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write_reg_word (CR_MAC_MACCR, macCtrl.value);
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pause(2);
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}
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#if defined(TCSUPPORT_MULTI_UPGRADE) || defined(TCSUPPORT_MULTI_BOOT)
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static void pause2(int ms)
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{
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unsigned int i;
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for (i = 0; i < ms * 100000; i++)
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;
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}
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void resetSwMAC(void)
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{
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macCtrlReg_t macCtrl;
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// Disable DMA Enable
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macCtrl.value = 0;
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write_reg_word (CR_MAC_MACCR, macCtrl.value);
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pause2(2);
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// Reset Mac
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macCtrl.bits.sw_rst = 1;
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write_reg_word (CR_MAC_MACCR, macCtrl.value);
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pause2(2);
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}
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#endif
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PUBLIC void
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macControllerStop(macAdapter_t *mac_p)
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{
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macCtrlReg_t macCtrl;
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macCtrl.value = VPint(CR_MAC_MACCR);
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/* disable DMA tx& rx */
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macCtrl.bits.rdma_en = 0;
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macCtrl.bits.xdma_en = 0;
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/* disable mac tx& rx */
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macCtrl.bits.rcv_en = 0;
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macCtrl.bits.xmt_en = 0;
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VPint(CR_MAC_MACCR) = macCtrl.value;
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}
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PUBLIC void
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macDefaultParaSet
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(
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macAdapter_t *mac_p
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)
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{
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mac_p->rxDescrSize = MAC_RXDESCP_SIZE;
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mac_p->txDescrSize = MAC_TXDESCP_SIZE;
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mac_p->rxRingSize = MAC_RXDESCP_NO;
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mac_p->txRingSize = MAC_TXDESCP_NO;
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}
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PUBLIC void
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macGetMacAddr(
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macAdapter_t *mac_p, unsigned char *macAddr
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)
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{
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int i;
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for (i = 0; i < 6; i++)
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mac_p->macAddr[i] = macAddr[i];
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}
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PRIVATE BOOLEAN
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macDrvDescripInit
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(
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macAdapter_t *mac_p
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)
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{
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macRxDescr_t *pRxDescp;
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macTxDescr_t *pTxDescp;
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uint32 physicalAddr;
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uint32 i;
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sk_buff *skb;
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mac_p->txDescrRingBaseVAddr = K0_TO_K1((uint32)&mac_p->macMemPool_p->descrPool[0]);
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mac_p->rxDescrRingBaseVAddr = mac_p->txDescrRingBaseVAddr + (mac_p->txDescrSize * mac_p->txRingSize);
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/* init. tx descriptor, don't allocate memory */
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pTxDescp = (macTxDescr_t*) mac_p->txDescrRingBaseVAddr;
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mac_p->txCurrDescp = pTxDescp;
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for ( i = 0 ; i < mac_p->txRingSize ; i++, pTxDescp++ )
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{
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// Init descriptor
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pTxDescp->tdes0.word = 0;
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pTxDescp->tdes1.word = 0;
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pTxDescp->tdes2.word = 0;
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// Assign flag
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pTxDescp->tdes0.bits.ownerDma = 0; /* owned by CPU */
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pTxDescp->tdes1.bits.sw_txtag_en = 0; /* SW Tag */
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pTxDescp->tdes1.bits.ipcs_en = 0; /* IP Chksum */
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pTxDescp->tdes1.bits.vtag_en = 0; /* VLAN Tag */
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pTxDescp->skb = NULL;
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}
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/* init. Rx descriptor, allocate memory for each descriptor */
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pRxDescp = (macRxDescr_t*) mac_p->rxDescrRingBaseVAddr;
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for( i = 0 ; i< mac_p->rxRingSize ; i++, pRxDescp++)
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{
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// Init Descriptor
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pRxDescp->rdes0.word = 0;
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pRxDescp->rdes1.word = 0;
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pRxDescp->rdes2.word = 0;
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// Assign flag
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pRxDescp->rdes0.bits.ownerDma = 1; /* owned by DMA */
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pRxDescp->rdes1.bits.rxBufSize = 1776;
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if( (skb = alloc_skb(2000)) == NULL ){
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printf("skb is null\n");
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}
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skb_reserve(skb, 2);
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pRxDescp->rdes2.buf_p = K1_TO_PHY(skb->data);
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pRxDescp->skb = skb;
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}
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mac_p->txCurrentDescp = 0;
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mac_p->txUnReleasedDescp = 0;
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mac_p->txUnReleasedBufCnt = 0;
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mac_p->rxCurrentDescp = 0;
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return TRUE;
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}
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void
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macPhyReset(
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void
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)
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{
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if (isTC3162U) {
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VPint(CR_AHB_SSR) |= (1<<11)|(1<<10)|(1<<9)|(1<<8);
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pause(10);
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}else if(isRT63260){
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VPint(CR_AHB_SSR) |= (1<<24);
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pause(10);
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}
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eth_gpioReset();
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miiStationWrite(mac_p->enetPhyAddr, PHY_CONTROL_REG, PHY_RESET );
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miiStationWrite(mac_p->enetPhyAddr, PHY_CONTROL_REG, MIIDR_AUTO_NEGOTIATE );
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}
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PRIVATE void macIMRMask(void)
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{
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macIntrMaskReg_t macIntrMask;
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macIntrMask.value = 0;
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macIntrMask.bits.rpkt_finish = 1;
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#if 0
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macIntrMask.bits.rpkt_ok_by_thrhold = 0;
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macIntrMask.bits.rpkt_ok_by_timeout = 0;
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macIntrMask.bits.xpkt_ok_by_thrhold = 0;
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macIntrMask.bits.xpkt_ok_by_timeout = 0;
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macIntrMask.bits.norxbuf = 1;
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macIntrMask.bits.notxbuf = 1;
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macIntrMask.bits.xpkt_finish = 1;
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macIntrMask.bits.xpkt_lost = 1;
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macIntrMask.bits.rpkt_lost = 1;
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macIntrMask.bits.xpkt_save = 1;
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macIntrMask.bits.rpkt_save = 1;
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macIntrMask.bits.ahb_err = 1;
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macIntrMask.bits.physts_chg = 1;
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#endif
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write_reg_word(CR_MAC_IMR, macIntrMask.value);
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}
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PRIVATE void macSetIntTimer(void)
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{
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mac_intr_timer_ctrl_reg_t macIntrTimerCtrl;
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macIntrTimerCtrl.value = 0;
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write_reg_word (CR_MAC_ITC, macIntrTimerCtrl.value);
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}
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// Assign Tx Rx Descriptor Control Registers
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PRIVATE void macSetDMADescrCtrlReg(macAdapter_t *mac_p)
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{
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write_reg_word(CR_MAC_TXR_BADR, K1_TO_PHY( mac_p->txDescrRingBaseVAddr));
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write_reg_word(CR_MAC_RXR_BADR, K1_TO_PHY( mac_p->rxDescrRingBaseVAddr));
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VPint(CR_MAC_TXR_SIZE) = mac_p->txRingSize;
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VPint(CR_MAC_RXR_SIZE) = mac_p->rxRingSize;
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VPint(CR_MAC_TXDESP_SIZE) = mac_p->txDescrSize;
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VPint(CR_MAC_RXDESP_SIZE) = mac_p->rxDescrSize;
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}
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PRIVATE void macSetMACCR
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(
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macAdapter_t *map_p
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)
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{
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macCtrlReg_t macCtrl;
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// --- configure MAC ---
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// clear reg
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//macCtrl.value = 0x3df23;
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macCtrl.value = 0x0;
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// set flag
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macCtrl.bits.rx_broadpkt = 1;
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macCtrl.bits.rx_multipkt = 1;
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macCtrl.bits.fulltx = 1;
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macCtrl.bits.crc_apd = 1;
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macCtrl.bits.mdc_sel = 0;
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macCtrl.bits.rcv_all = 1;
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macCtrl.bits.rx_ftl = 1;
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macCtrl.bits.rx_runt = 1;
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macCtrl.bits.ht_multi_en = 1;
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macCtrl.bits.rcv_en = 0;
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macCtrl.bits.l2_mode = 1;
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macCtrl.bits.enrx_in_halftx = 0;
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macCtrl.bits.xmt_en = 0;
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macCtrl.bits.crc_dis = 0;
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macCtrl.bits.loop_en = 0;
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macCtrl.bits.sw_rst = 0;
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macCtrl.bits.rdma_en = 0;
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macCtrl.bits.xdma_en = 0;
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macCtrl.bits.txfifo_thr = 0x0e;
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macCtrl.bits.rx_untag = 0;
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macCtrl.bits.drop_local = 0;
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write_reg_word (CR_MAC_MACCR, macCtrl.value);
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}
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PRIVATE void macSetMacReg
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(
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macAdapter_t *mac_p
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)
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{
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write_reg_word(CR_MAC_MADR,mac_p->macAddr[0]<<8 | mac_p->macAddr[1]<<0);
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write_reg_word(CR_MAC_LADR,mac_p->macAddr[2]<<24 | mac_p->macAddr[3]<<16 | \
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mac_p->macAddr[4]<<8 | mac_p->macAddr[5]<<0);
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}
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PUBLIC int
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macDrvRegInit(
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macAdapter_t *mac_p
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)
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{
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// ----- setup interrupt mask ---
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// ---- Setup HASH table------------------------------------------
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// -----Setup Interrupt Timer-------------------------------------
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// -----Setup AUTO polling timer----------------------------------
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// ---- Setup DMA burst and arbitration---------------------------
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// -----Setup DMA Descriptor Base Address Assign------------------
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// -----Setup MACCR-----------------------------------------------
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macResetSwMAC();
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macIMRMask();
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//macSetHashTable();
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macSetIntTimer();
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//macSetAutoPollTmr();
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//macSetupDMABurstArbitration();
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macSetDMADescrCtrlReg(mac_p);
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macSetMACCR(mac_p);
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// --- setup MAC address ---
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macSetMacReg(mac_p);
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return 0;
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}
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PUBLIC void
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macDrvStart
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(
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void
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)
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{
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macCtrlReg_t macCtrl;
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macCtrl.value = VPint(CR_MAC_MACCR);
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/* enable DMA tx& rx */
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macCtrl.bits.rdma_en = 1;
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macCtrl.bits.xdma_en = 1;
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/* enable mac tx& rx */
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macCtrl.bits.rcv_en = 1;
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macCtrl.bits.xmt_en = 1;
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VPint(CR_MAC_MACCR) = macCtrl.value;
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}
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PUBLIC int
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macSetRxMode(
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void
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)
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{
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macCtrlReg_t mac_cr;
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mac_cr.value=tc_inl(CR_MAC_MACCR); /* Accept all packet */
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mac_cr.bits.rcv_all=0;
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mac_cr.bits.ht_multi_en=0;
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mac_cr.bits.rx_broadpkt=1;
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mac_cr.bits.rcv_en=1;
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tc_outl(CR_MAC_MACCR, mac_cr.value);
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return 0;
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} /* macSetRxMode */
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PRIVATE macTxDescr_t*
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macTxRingProc
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(
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macAdapter_t *mac_p
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)
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{
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uint32 i;
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volatile macTxDescr_t *pTxDescp;
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pTxDescp = ((macTxDescr_t*)mac_p->txDescrRingBaseVAddr) + mac_p->txUnReleasedDescp;
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while ( mac_p->txUnReleasedBufCnt != 0 )
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{
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if ( (pTxDescp->tdes0.word)&(1<<31) )
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{
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return 0; // owned by MAC engine, something wrong here!
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}
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free_skb(pTxDescp->skb);
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pTxDescp->tdes2.buf_p = NULL;
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pTxDescp->skb = NULL;
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if ( mac_p->txUnReleasedDescp == ( mac_p->txRingSize - 1) )
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{
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mac_p->txUnReleasedDescp = 0;
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}
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else
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{
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mac_p->txUnReleasedDescp++;
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}
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mac_p->txUnReleasedBufCnt--;
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pTxDescp = ((macTxDescr_t*)mac_p->txDescrRingBaseVAddr) + mac_p->txUnReleasedDescp;
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} // while
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return (macTxDescr_t*)pTxDescp;
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}
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PUBLIC void
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macRxRingProc
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(
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void
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)
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{
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volatile macRxDescr_t *rxDescrp;
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uint32 frameSize;
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sk_buff *newMbp, *oldMbp;
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uint32 procFrameCnt = 0;
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uint32 rdes0_error_check, rdes1_error_check;
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uint32 i = 0;
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uint8* pdata;
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rxDescrp = ((macRxDescr_t*)mac_p->rxDescrRingBaseVAddr) + mac_p->rxCurrentDescp;
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rdes0_error_check = (1<<27|1<<22|1<<21|1<<20|1<<19|1<<18);
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rdes1_error_check = 0;
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while ((rxDescrp->rdes0.word & (1<<31)) == 0) // ownerDMA for TCMAC
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{
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if ( (rxDescrp->rdes0.word & rdes0_error_check) == 0 &&
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(rxDescrp->rdes1.word & rdes1_error_check) == 0 )
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{
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// For removing Rx VLAN tag, we need to check if the remain length
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// is not smaller than minimun packet length.
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// rxDescrp->rdes0.bits.vlan_hit
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if (rxDescrp->rdes0.word & (1<<30))
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{
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frameSize = rxDescrp->rdes0.bits.rfl;
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frameSize = (frameSize > 60) ? frameSize : 60;
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}
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else
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frameSize = rxDescrp->rdes0.bits.rfl;
|
|
|
|
/* lino: make VLAN friendly */
|
|
if ( (frameSize < 60) || (frameSize > 1518) )
|
|
{
|
|
// Discard this packet & Repost this mbuf
|
|
(volatile sk_buff *)newMbp = (volatile sk_buff *)(rxDescrp->skb);
|
|
goto DISCARD;
|
|
}
|
|
|
|
(volatile sk_buff *)oldMbp = (volatile sk_buff *)(rxDescrp->skb);
|
|
oldMbp->len = frameSize;
|
|
|
|
newMbp = (sk_buff *)alloc_skb(2000);
|
|
if ( !newMbp ) { /* faild to allocate more mbuf-> drop this pkt */
|
|
newMbp = oldMbp;
|
|
goto RECVOK;
|
|
}
|
|
skb_reserve(newMbp, 2);
|
|
|
|
eth_rcv(oldMbp);
|
|
|
|
DISCARD:
|
|
|
|
RECVOK:
|
|
|
|
rxDescrp->rdes2.buf_p = K1_TO_PHY(newMbp->data);
|
|
rxDescrp->skb = newMbp;
|
|
} else {
|
|
prom_printf("error\n");
|
|
prom_printf("rdes0=%08x\n", rxDescrp->rdes0.word);
|
|
prom_printf("rdes1=%08x\n", rxDescrp->rdes1.word);
|
|
prom_printf("rdes2=%08x\n", rxDescrp->rdes2.word);
|
|
prom_printf("rdes3=%08x\n", rxDescrp->rdes3.word);
|
|
}
|
|
|
|
rxDescrp->rdes0.word |= (1<<31);
|
|
|
|
/* next descriptor*/
|
|
if ( mac_p->rxCurrentDescp == ( mac_p->rxRingSize - 1 ))
|
|
mac_p->rxCurrentDescp = 0;
|
|
else
|
|
mac_p->rxCurrentDescp++;
|
|
|
|
rxDescrp = ((macRxDescr_t*)mac_p->rxDescrRingBaseVAddr) + mac_p->rxCurrentDescp;
|
|
} /* while loop */
|
|
|
|
VPint(CR_MAC_RXR_SWIDX) = mac_p->rxCurrentDescp;
|
|
}
|
|
|
|
void mac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|
{
|
|
macIntrStatusReg_t isr;
|
|
|
|
VPint(CR_INTC_IMR) &= ~(1<<MAC_INT);
|
|
// -------Read MACCR--------------------------------
|
|
isr.value=tc_inl(CR_MAC_ISR);
|
|
|
|
#if 0
|
|
if(isr.bits.physts_chg )prom_printf("\r\n--->PHYSTS_CHG ");
|
|
if(isr.bits.ahb_err )prom_printf("\r\n--->AHB_ERR ");
|
|
if(isr.bits.rpkt_lost )prom_printf("\r\n--->RPKT_LOST ");
|
|
// if(isr.bits.rpkt_save )prom_printf("\r\n--->RPKT_SAVE ");
|
|
if(isr.bits.xpkt_lost )prom_printf("\r\n--->XPKT_LOST ");
|
|
// if(isr.bits.xpkt_finish )prom_printf("\r\n--->XPKT_FINISH ");
|
|
if(isr.bits.notxbuf )prom_printf("\r\n--->NOTXBUF ");
|
|
// if(isr.bits.xpkt_save )prom_printf("\r\n--->XPKT_SAVE ");
|
|
if(isr.bits.norxbuf )prom_printf("\r\n--->NORXBUF ");
|
|
if(isr.bits.rpkt_finish )prom_printf("\r\n--->RPKT_FINISH ");
|
|
#endif
|
|
|
|
// ----------Packet Received----------------------
|
|
if( isr.bits.rpkt_finish)
|
|
{
|
|
macRxRingProc();
|
|
}
|
|
SKIP:
|
|
VPint(CR_INTC_IMR) |= (1<<MAC_INT);
|
|
MAC_RX_POLL_DEMAND_(1);
|
|
}
|
|
|
|
int tc3162_eth_send(sk_buff *skb)
|
|
{
|
|
macTxDescr_t *currDescrp = NULL;
|
|
uint32 length = skb->len;
|
|
uint8 *bufAddrp = skb->data;
|
|
macTxDescr_t *tx; // just for debug only
|
|
uint32 i;
|
|
|
|
if( skb->data == NULL ){
|
|
printf("\n\rTx a empty mbuf");
|
|
}
|
|
|
|
macTxRingProc(mac_p);
|
|
|
|
if ( mac_p->txUnReleasedBufCnt == mac_p->txRingSize )
|
|
{
|
|
free_skb(skb);
|
|
return 1;
|
|
}
|
|
|
|
/* ----- Get the transmit descriptor ----- */
|
|
currDescrp = ((macTxDescr_t*)mac_p->txDescrRingBaseVAddr) + mac_p->txCurrentDescp;
|
|
|
|
if( (currDescrp->tdes0.word)&(1<<31) )
|
|
{
|
|
free_skb(skb);
|
|
return 1;
|
|
}
|
|
|
|
// tx buffer size
|
|
currDescrp->tdes0.word = 0;
|
|
/* clear all except edotr, fts, lts */
|
|
currDescrp->tdes1.word &= (1<<31|1<<28|1<<27);
|
|
currDescrp->tdes1.word |= (length&0x000007ff);
|
|
|
|
currDescrp->tdes2.buf_p = K1_TO_PHY(skb->data);
|
|
currDescrp->skb = skb;
|
|
|
|
currDescrp->tdes0.word |= (1<<31);
|
|
|
|
if( mac_p->txCurrentDescp == ( mac_p->txRingSize - 1 ))
|
|
{
|
|
mac_p->txCurrentDescp = 0;
|
|
}
|
|
else
|
|
{
|
|
mac_p->txCurrentDescp ++;
|
|
}
|
|
|
|
mac_p->txUnReleasedBufCnt++;
|
|
|
|
MAC_TX_POLL_DEMAND_(1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct irqaction mac_irq = {mac_interrupt, NULL, 0, "mac", NULL, NULL};
|
|
|
|
|
|
int tc3162_eth_init(unsigned char *mac_addr)
|
|
{
|
|
int i;
|
|
|
|
macControllerStop(mac_p);
|
|
|
|
mac_p->macMemPool_p = &enetMemPool;
|
|
mac_p->enetPhyAddr = 0;
|
|
|
|
/* ----- Set up the paramters ----- */
|
|
macDefaultParaSet(mac_p);
|
|
|
|
macGetMacAddr(mac_p, mac_addr);
|
|
macDrvDescripInit(mac_p);
|
|
macPhyReset();
|
|
pause(100);
|
|
|
|
macSearchPhyAddr(mac_p);
|
|
/* ----- Initialize the SEEQ 80225 phy chip(enet phy) ----- */
|
|
if (macSetUpPhy(mac_p)){
|
|
return -1;
|
|
}
|
|
|
|
macDrvRegInit(mac_p);
|
|
|
|
request_IRQ(MAC_INT, &mac_irq, NULL);
|
|
macDrvStart();
|
|
|
|
macSetRxMode();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int tc3162_eth_exit(void)
|
|
{
|
|
return 0;
|
|
}
|