757 lines
24 KiB
C
Executable File
757 lines
24 KiB
C
Executable File
/*
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** $Id: //BBN_Linux/Branch/Branch_for_MT7520_20120528/tclinux_phoenix/bootrom/bootram/net/femac.h#2 $
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*/
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/************************************************************************
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*
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* Copyright (C) 2008 Trendchip Technologies, Corp.
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* All Rights Reserved.
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*
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* Trendchip Confidential; Need to Know only.
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* Protected as an unpublished work.
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*
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* The computer program listings, specifications and documentation
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* herein are the property of Trendchip Technologies, Co. and shall
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* not be reproduced, copied, disclosed, or used in whole or in part
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* for any reason without the prior express written permission of
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* Trendchip Technologeis, Co.
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*
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*************************************************************************/
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/*
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** $Log: femac.h,v $
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** Revision 1.1.2.5 2011/08/02 06:07:38 lino
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** add RT63365 support: SDRAM/DDR1/DDR2 parameter
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**
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** Revision 1.1.2.4 2011/05/10 02:28:27 lino
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** add RT63365 frame engine support
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**
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** Revision 1.1.2.3 2011/04/20 10:53:00 lino
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** add RT63365 support
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**
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** Revision 1.1.2.2 2011/04/20 09:57:27 lino
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** add RT63365 support
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**
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** Revision 1.1.2.1 2011/04/20 02:46:32 lino
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** add RT63365 support
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**
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** Revision 1.1.1.1.14.1 2010/09/28 12:53:37 lino
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** add RT63165 support
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**
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** Revision 1.1.1.1 2010/04/09 09:31:07 feiyan
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** New TC Linux Make Flow Trunk
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**
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** Revision 1.1.1.1 2009/12/17 01:47:29 josephxu
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** 20091217, from Hinchu ,with VoIP
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**
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*/
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#ifndef _FEMAC_63365_H
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#define _FEMAC_63365_H
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#include <asm/tc3162.h>
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#include "skbuff.h"
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#define MAC_TXDESCP_NO 64 /* Max tx buffer Cnts , default=64 */
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#define MAC_RXDESCP_NO 64 /* Max rx buffer Cnts , default=64 */
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#define MAC_RXDESCP_SIZE 16 /* 4 DWords */
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#define MAC_TXDESCP_SIZE 16 /* 4 DWords */
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#define K0_TO_K1(x) (((uint32)x) | 0xa0000000)
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#define K1_TO_PHY(x) (((uint32)x) & 0x1fffffff)
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/* ----- PHY-Chip Definition ----- */
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#define PHY_CONTROL_REG 0 /* MII Control Register */
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#define PHY_RESET 0x8000
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#define PHY_POWER_DOWN 0x0800
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#define PHY_AN_ENABLE 0x1000
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#define PHY_RESTART_AN 0x200
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#define PHY_SPEED_SELECT_100 0x2000
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#define PHY_FULL_DUPLEX 0x100
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#define PHY_ISOLATE 0x400
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#define PHY_LOOPBACK 0x4000
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#define PHY_STATUS_REG 1 /* MII Status Register */
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#define PHY_AN_COMPLETE 0x0020
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#define PHY_LINK_STATUS 0x0004
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#define PHY_ID_REG1 2 /* Identifier register 1 */
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#define PHY_ID_REG2 3 /* Identifier register 2 */
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#define PHY_REMOTE_CAP_REG 5 /* Auto-Negotiation Link Partner Ability Reg */
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#define PHY_100_BASE_T4 0x200
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#define PHY_100_BASE_TX_FD 0x100
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#define PHY_100_BASE_TX_HD 0x80
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#define PHY_10_BASE_T_FD 0x40
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#define PHY_10_BASE_T_HD 0x20
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#define PHY_CONFIG_REG 16
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#define PHY_TP_LOOPBACK 0x0100
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#define MAC_STATISTIC_ON 1
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#define MAC_STATISTIC_OFF 0
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/*****************************
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* Ethernet Module Registers *
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*****************************/
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#define FE_BASE 0xBFB50000
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#define MDIO_ACCESS (FE_BASE + 0x00)
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#define MDIO_CFG (FE_BASE + 0x04)
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#define FE_DMA_GLO_CFG (FE_BASE + 0x08)
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#define FE_RST_GLO (FE_BASE + 0x0C)
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#define FE_INT_STATUS (FE_BASE + 0x10)
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#define FE_INT_ENABLE (FE_BASE + 0x14)
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#define FC_DROP_STA (FE_BASE + 0x18)
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#define FOE_TS_T (FE_BASE + 0x1C)
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#define FE_VLAN_ID(n) (FE_BASE + 0xa8 + (n)*4)
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#define PDMA_BASE (FE_BASE + 0x0800)
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#define TX_BASE_PTR(n) (PDMA_BASE + (n)*0x10 + 0x000)
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#define TX_MAX_CNT(n) (PDMA_BASE + (n)*0x10 + 0x004)
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#define TX_CTX_IDX(n) (PDMA_BASE + (n)*0x10 + 0x008)
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#define TX_DTX_IDX(n) (PDMA_BASE + (n)*0x10 + 0x00C)
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#define RX_BASE_PTR(n) (PDMA_BASE + (n)*0x10 + 0x100)
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#define RX_MAX_CNT(n) (PDMA_BASE + (n)*0x10 + 0x104)
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#define RX_CALC_IDX(n) (PDMA_BASE + (n)*0x10 + 0x108)
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#define RX_DRX_IDX(n) (PDMA_BASE + (n)*0x10 + 0x10C)
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#define PDMA_INFO (PDMA_BASE + 0x200)
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#define PDMA_GLO_CFG (PDMA_BASE + 0x204)
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#define PDMA_RST_IDX (PDMA_BASE + 0x208)
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#define DLY_INT_CFG (PDMA_BASE + 0x20C)
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#define FREEQ_THRES (PDMA_BASE + 0x210)
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#define INT_STATUS (PDMA_BASE + 0x220)
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#define INT_MASK (PDMA_BASE + 0x228)
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#define SCH_Q01_CFG (PDMA_BASE + 0x280)
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#define SCH_Q23_CFG (PDMA_BASE + 0x284)
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#define GDMA1_BASE (FE_BASE + 0x0020)
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#define GDMA1_FWD_CFG (GDMA1_BASE + 0x00)
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#define GDMA1_SCH_CFG (GDMA1_BASE + 0x04)
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#define GDMA1_SHRP_CFG (GDMA1_BASE + 0x08)
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#define GDMA1_MAC_ADRL (GDMA1_BASE + 0x0C)
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#define GDMA1_MAC_ADRH (GDMA1_BASE + 0x10)
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#define PSE_BASE (FE_BASE + 0x0040)
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#define PSE_FQFC_CFG (PSE_BASE + 0x00)
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#define CDMA_FC_CFG (PSE_BASE + 0x04)
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#define GDMA1_FC_CFG (PSE_BASE + 0x08)
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#define GDMA2_FC_CFG (PSE_BASE + 0x0C)
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#define CDMA_OQ_STA (PSE_BASE + 0x10)
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#define GDMA1_OQ_STA (PSE_BASE + 0x14)
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#define GDMA2_OQ_STA (PSE_BASE + 0x18)
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#define PSE_IQ_STA (PSE_BASE + 0x1C)
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#define GDMA2_BASE (FE_BASE + 0x0060)
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#define GDMA2_FWD_CFG (GDMA2_BASE + 0x00)
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#define GDMA2_SCH_CFG (GDMA2_BASE + 0x04)
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#define GDMA2_SHRP_CFG (GDMA2_BASE + 0x08)
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#define GDMA2_MAC_ADRL (GDMA2_BASE + 0x0C)
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#define GDMA2_MAC_ADRH (GDMA2_BASE + 0x10)
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#define CDMA_BASE (FE_BASE + 0x0080)
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#define CDMA_CSG_CFG (CDMA_BASE + 0x00)
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#define CDMA_SCH_CFG (CDMA_BASE + 0x04)
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#define GDMA_CNT_BASE (FE_BASE + 0x0400)
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#define GDMA_TX_GBCNT1 (GDMA_CNT_BASE + 0x300)
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#define GDMA_TX_GPCNT1 (GDMA_CNT_BASE + 0x304)
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#define GDMA_TX_SKIPCNT1 (GDMA_CNT_BASE + 0x308)
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#define GDMA_TX_COLCNT1 (GDMA_CNT_BASE + 0x30C)
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#define GDMA_RX_GBCNT1 (GDMA_CNT_BASE + 0x320)
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#define GDMA_RX_GPCNT1 (GDMA_CNT_BASE + 0x324)
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#define GDMA_RX_OERCNT1 (GDMA_CNT_BASE + 0x328)
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#define GDMA_RX_FERCNT1 (GDMA_CNT_BASE + 0x32C)
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#define GDMA_RX_SERCNT1 (GDMA_CNT_BASE + 0x330)
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#define GDMA_RX_LERCNT1 (GDMA_CNT_BASE + 0x334)
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#define GDMA_RX_CERCNT1 (GDMA_CNT_BASE + 0x338)
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#define GDMA_RX_FCCNT1 (GDMA_CNT_BASE + 0x33C)
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/********************************
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* Giga Switch Module Registers *
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********************************/
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#define GSW_BASE 0xBFB58000
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#define GSW_ARL_BASE (GSW_BASE + 0x0000)
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#define GSW_BMU_BASE (GSW_BASE + 0x1000)
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#define GSW_PORT_BASE (GSW_BASE + 0x2000)
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#define GSW_MAC_BASE (GSW_BASE + 0x3000)
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#define GSW_MIB_BASE (GSW_BASE + 0x4000)
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#define GSW_CFG_BASE (GSW_BASE + 0x7000)
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#define GSW_PSC(n) (GSW_PORT_BASE + (n)*0x100 + 0x0C)
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#define GSW_MFC (GSW_ARL_BASE + 0x10)
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#define GSW_PMCR(n) (GSW_MAC_BASE + (n)*0x100)
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#define GSW_PMSR(n) (GSW_MAC_BASE + (n)*0x100 + 0x08)
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#define GSW_SMACCR0 (GSW_MAC_BASE + 0xe4)
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#define GSW_SMACCR1 (GSW_MAC_BASE + 0xe8)
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#define GSW_ESR(n) (GSW_MIB_BASE + (n)*0x100 + 0x00)
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#define GSW_INTS(n) (GSW_MIB_BASE + (n)*0x100 + 0x04)
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#define GSW_TGPC(n) (GSW_MIB_BASE + (n)*0x100 + 0x10)
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#define GSW_TBOC(n) (GSW_MIB_BASE + (n)*0x100 + 0x14)
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#define GSW_TGOC(n) (GSW_MIB_BASE + (n)*0x100 + 0x18)
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#define GSW_TEPC(n) (GSW_MIB_BASE + (n)*0x100 + 0x1C)
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#define GSW_RGPC(n) (GSW_MIB_BASE + (n)*0x100 + 0x20)
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#define GSW_RBOC(n) (GSW_MIB_BASE + (n)*0x100 + 0x24)
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#define GSW_RGOC(n) (GSW_MIB_BASE + (n)*0x100 + 0x28)
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#define GSW_REPC1(n) (GSW_MIB_BASE + (n)*0x100 + 0x2C)
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#define GSW_REPC2(n) (GSW_MIB_BASE + (n)*0x100 + 0x30)
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#define GSW_MIBCNTEN (GSW_MIB_BASE + 0x800)
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#define GSW_AECNT1 (GSW_MIB_BASE + 0x804)
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#define GSW_AECNT2 (GSW_MIB_BASE + 0x808)
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#define GSW_CFG_PPSC (GSW_CFG_BASE + 0x0)
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#define GSW_CFG_PIAC (GSW_CFG_BASE + 0x4)
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#define GSW_CFG_GPC (GSW_CFG_BASE + 0x14)
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/***************************************
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* Ethernet Module Register Definition *
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***************************************/
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/* RSTCTRL2 */
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#define EPHY_RST (1<<24)
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#define ESW_RST (1<<23)
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#define FE_RST (1<<21)
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/* FE_VLAN_ID */
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#define VLAN_ID1_SHIFT (16)
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#define VLAN_IDl (0xfff<<VLAN_ID1_SHIFT)
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#define VLAN_ID0_SHIFT (0)
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#define VLAN_ID0 (0xfff<<VLAN_ID0_SHIFT)
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/* PDMA_GLO_CFG */
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#define PDMA_BYTE_SWAP (1<<31)
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#define PDMA_BIG_ENDIAN (1<<7)
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#define TX_WB_DDONE (1<<6)
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#define PDMA_BT_SIZE_SHIFT (4)
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#define PDMA_BT_SIZE (0x3<<PDMA_BT_SIZE_SHIFT)
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#define RX_DMA_BUSY (1<<3)
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#define RX_DMA_EN (1<<2)
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#define TX_DMA_BUSY (1<<1)
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#define TX_DMA_EN (1<<0)
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#define PDMA_BT_SIZE_4DW (0)
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#define PDMA_BT_SIZE_8DW (1)
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#define PDMA_BT_SIZE_16DW (2)
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#define PDMA_BT_SIZE_32DW (3)
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/* PDMA_RST_IDX */
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#define RST_DRX_IDX(n) (1<<(16+(n)))
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#define RST_DTX_IDX(n) (1<<(n))
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/* DLY_INT_CFG */
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#define TXDLY_INT_EN (1<<31)
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#define TXMAX_PINT_SHIFT (24)
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#define TXMAX_PINT (0x7f<<TXMAX_PINT_SHIFT)
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#define TXMAX_PTIME_SHIFT (16)
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#define TXMAX_PTIME (0xff<<TXMAX_PTIME_SHIFT)
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#define RXDLY_INT_EN (1<<15)
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#define RXMAX_PINT_SHIFT (8)
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#define RXMAX_PINT (0x7f<<RXMAX_PINT_SHIFT)
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#define RXMAX_PTIME_SHIFT (0)
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#define RXMAX_PTIME (0xff<<RXMAX_PTIME_SHIFT)
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/* INT_STATUS or INT_MASK */
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#define RX_COHERENT (1<<31)
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#define RX_DLY_INT (1<<30)
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#define TX_COHERENT (1<<29)
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#define TX_DLY_INT (1<<28)
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#define RX_DONE_INT1 (1<<17)
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#define RX_DONE_INT0 (1<<16)
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#define TX_DONE_INT3 (1<<3)
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#define TX_DONE_INT2 (1<<2)
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#define TX_DONE_INT1 (1<<1)
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#define TX_DONE_INT0 (1<<0)
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/* GDMA1_FWD_CFG or GDMA2_FWD_CFG */
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#define GDM_JMB_LEN_SHIFT (28)
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#define GDM_JMB_LEN (0xf<<GDM_JMB_LEN_SHIFT)
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#define GDM_20US_TICK_SLT (1<<25)
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#define GDM_TCI_81XX (1<<24)
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#define GDM_DROP_256B (1<<23)
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#define GDM_ICS_EN (1<<22)
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#define GDM_TCS_EN (1<<21)
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#define GDM_UCS_EN (1<<20)
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#define GDM_JMB_EN (1<<19)
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#define GDM_DISPAD (1<<18)
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#define GDM_DISCRC (1<<17)
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#define GDM_STRPCRC (1<<16)
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#define GDM_UFRC_P_SHIFT (12)
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#define GDM_UFRC_P (0x7<<GDM_UFRC_P_SHIFT)
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#define GDM_BFRC_P_SHIFT (8)
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#define GDM_BFRC_P (0x7<<GDM_BFRC_P_SHIFT)
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#define GDM_MFRC_P_SHIFT (4)
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#define GDM_MFRC_P (0x7<<GDM_MFRC_P_SHIFT)
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#define GDM_OFRC_P_SHIFT (0)
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#define GDM_OFRC_P (0x7<<GDM_MFRC_P_SHIFT)
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/* define GDMA port */
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#define GDM_P_CPU (0)
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#define GDM_P_GDMA1 (1)
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#define GDM_P_GDMA2 (2)
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#define GDM_P_PPE (6)
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#define GDM_P_DISCARD (7)
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/* CDMA_CSG_CFG */
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#define INS_VLAN_SHIFT (16)
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#define INS_VLAN (0xffff<<INS_VLAN_SHIFT)
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#define ICS_GEN_EN (1<<2)
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#define UCS_GEN_EN (1<<1)
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#define TCS_GEN_EN (1<<0)
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/* GSW_MFC */
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#define MFC_BC_FFP_SHIFT (24)
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#define MFC_BC_FFP (0xff<<MFC_BC_FFP_SHIFT)
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#define MFC_UNM_FFP_SHIFT (16)
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#define MFC_UNM_FFP (0xff<<MFC_UNM_FFP_SHIFT)
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#define MFC_UNU_FFP_SHIFT (8)
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#define MFC_UNU_FFP (0xff<<MFC_UNU_FFP_SHIFT)
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#define MFC_CPU_EN (1<<7)
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#define MFC_CPU_PORT_SHIFT (4)
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#define MFC_CPU_PORT (0x7<<MFC_CPU_PORT_SHIFT)
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#define MFC_MIRROR_EN (1<<3)
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#define MFC_MIRROR_PORT_SHIFT (0)
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#define MFC_MIRROT_PORT (0x7<<MFC_MIRROR_PORT_SHIFT)
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/* GSW_PMCR */
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#define IPG_CFG_PN_SHIFT (18)
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#define IPG_CFG_PN (0x3<<IPG_CFG_PN_SHIFT)
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#define EXT_PHY_PN (1<<17)
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#define MAC_MODE_PN (1<<16)
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#define FORCE_MODE_PN (1<<15)
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#define MAC_TX_EN_PN (1<<14)
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#define MAC_RX_EN_PN (1<<13)
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#define RGMII_MODE_PN (1<<12)
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#define BKOFF_EN_PN (1<<9)
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#define BACKPR_EN_PN (1<<8)
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#define ENABLE_EEE1G_PN (1<<7)
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#define ENABLE_EEE100_PN (1<<6)
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#define ENABLE_RX_FC_PN (1<<5)
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#define ENABLE_TX_FC_PN (1<<4)
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#define FORCE_SPD_PN_SHIFT (2)
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#define FORCE_SPD_PN (0x3<<FORCE_SPD_PN_SHIFT)
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#define FORCE_DPX_PN (1<<1)
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#define FORCE_LNK_PN (1<<0)
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#define IPG_CFG_NORMAL (0)
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#define IPG_CFG_SHORT (1)
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#define PN_SPEED_10M (0)
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#define PN_SPEED_100M (1)
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#define PN_SPEED_1000M (2)
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/* GSW_PMSR */
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#define EEE1G_STS (1<<7)
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#define EEE100_STS (1<<6)
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#define RX_FC_STS (1<<5)
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#define TX_FC_STS (1<<4)
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#define MAC_SPD_STS_SHIFT (2)
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#define MAC_SPD_STS (0x3<<MAC_SPD_STS_SHIFT)
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#define MAC_DPX_STS (1<<1)
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#define MAC_LINK_STS (1<<0)
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/* GSW_TGPC */
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#define TX_BAD_CNT_SHIFT (16)
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#define TX_BAD_CNT (0xffff<<TX_BAD_CNT_SHIFT)
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#define TX_GOOD_CNT_SHIFT (0)
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#define TX_GOOD_CNT (0xffff<<TX_GOOD_CNT_SHIFT)
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/* GSW_RGPC */
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#define RX_BAD_CNT_SHIFT (16)
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#define RX_BAD_CNT (0xffff<<RX_BAD_CNT_SHIFT)
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#define RX_GOOD_CNT_SHIFT (0)
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#define RX_GOOD_CNT (0xffff<<RX_GOOD_CNT_SHIFT)
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/* GSW_REPC1 */
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#define RX_CTRL_DROP_CNT_SHIFT (16)
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#define RX_CTRL_DROP_CNT (0xffff<<RX_CTRL_DROP_CNT_SHIFT)
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#define RX_ING_DROP_CNT_SHIFT (0)
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#define RX_ING_DROP_CNT (0xffff<<RX_ING_DROP_CNT_SHIFT)
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/* GSW_REPC2 */
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#define RX_ARL_DROP_CNT_SHIFT (16)
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#define RX_ARL_DROP_CNT (0xffff<<RX_ARL_DROP_CNT_SHIFT)
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#define RX_FILTER_DROP_CNT_SHIFT (0)
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#define RX_FILTER_DROP_CNT (0xffff<<RX_FILTER_DROP_CNT_SHIFT)
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/* GSW_CFG_PPSC */
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#define PHY_AP_EN (1<<31)
|
|
#define PHY_PRE_EN (1<<30)
|
|
#define PHY_MDC_CFG_SHIFT (24)
|
|
#define PHY_MDC_CFG (0x3f<<PHY_MDC_CFG_SHIFT)
|
|
#define EMB_AN_EN (1<<23)
|
|
#define EEE_AN_EN_SHIFT (16)
|
|
#define EEE_AN_EN (16)
|
|
#define PHY_END_ADDR_SHIFT (8)
|
|
#define PHY_END_ADDR (0x1f<<PHY_END_ADDR_SHIFT)
|
|
#define PHY_ST_ADDR_SHIFT (0)
|
|
#define PHY_ST_ADDR (0x1f<<PHY_ST_ADDR_SHIFT)
|
|
|
|
/* GSW_CFG_PIAC */
|
|
#define PHY_ACS_ST (1<<31)
|
|
#define MDIO_REG_ADDR_SHIFT (25)
|
|
#define MDIO_REG_ADDR (0x1f<<MDIO_REG_ADDR_SHIFT)
|
|
#define MDIO_PHY_ADDR_SHIFT (20)
|
|
#define MDIO_PHY_ADDR (0x1f<<MDIO_PHY_ADDR_SHIFT)
|
|
#define MDIO_CMD_SHIFT (18)
|
|
#define MDIO_CMD (0x3<<MDIO_CMD_SHIFT)
|
|
#define MDIO_ST_SHIFT (16)
|
|
#define MDIO_ST (0x3<<MDIO_ST_SHIFT)
|
|
#define MDIO_RW_DATA_SHIFT (0)
|
|
#define MDIO_RW_DATA (0xffff<<MDIO_RW_DATA_SHIFT)
|
|
|
|
#define PHY_ACS_ST_START (1)
|
|
#define MDIO_CMD_WRITE (1)
|
|
#define MDIO_CMD_READ (2)
|
|
#define MDIO_ST_START (1)
|
|
|
|
/* GSW_CFG_GPC */
|
|
#define RX_CLK_MODE (1<<2)
|
|
|
|
//FPORT DEFINE
|
|
#define DPORT_CPU 0
|
|
#define DPORT_GDMA1 1
|
|
#define DPORT_GDMA2 2
|
|
#define DPORT_PPE 6
|
|
#define DPORT_DISCARD 7
|
|
|
|
/*=========================================
|
|
PDMA RX Descriptor Format define
|
|
=========================================*/
|
|
|
|
//-------------------------------------------------
|
|
|
|
typedef union {
|
|
struct _PDMA_RXD_INFO1_
|
|
{
|
|
unsigned int PDP0;
|
|
} bits;
|
|
uint32 word;
|
|
} PDMA_RXD_INFO1_T;
|
|
//-------------------------------------------------
|
|
|
|
typedef union {
|
|
struct _PDMA_RXD_INFO2_
|
|
{
|
|
#ifdef __BIG_ENDIAN
|
|
unsigned int DDONE_bit : 1;
|
|
unsigned int LS0 : 1;
|
|
unsigned int PLEN0 : 14;
|
|
unsigned int UN_USED : 1;
|
|
unsigned int LS1 : 1;
|
|
unsigned int PLEN1 : 14;
|
|
#else
|
|
unsigned int PLEN1 : 14;
|
|
unsigned int LS1 : 1;
|
|
unsigned int UN_USED : 1;
|
|
unsigned int PLEN0 : 14;
|
|
unsigned int LS0 : 1;
|
|
unsigned int DDONE_bit : 1;
|
|
#endif
|
|
} bits;
|
|
uint32 word;
|
|
} PDMA_RXD_INFO2_T;
|
|
//-------------------------------------------------
|
|
|
|
typedef union {
|
|
struct _PDMA_RXD_INFO3_
|
|
{
|
|
unsigned int UN_USE1;
|
|
} bits;
|
|
uint32 word;
|
|
} PDMA_RXD_INFO3_T;
|
|
//-------------------------------------------------
|
|
|
|
typedef union {
|
|
struct _PDMA_RXD_INFO4_
|
|
{
|
|
#ifdef __BIG_ENDIAN
|
|
unsigned int IPFVLD_bit : 1;
|
|
unsigned int L4FVLD_bit : 1;
|
|
unsigned int IPF : 1;
|
|
unsigned int L4F : 1;
|
|
unsigned int AIS : 1;
|
|
unsigned int SP : 3;
|
|
unsigned int AI : 8;
|
|
unsigned int UN_USE1 : 1;
|
|
unsigned int FVLD : 1;
|
|
unsigned int FOE_Entry : 14;
|
|
#else
|
|
unsigned int FOE_Entry : 14;
|
|
unsigned int FVLD : 1;
|
|
unsigned int UN_USE1 : 1;
|
|
unsigned int AI : 8;
|
|
unsigned int SP : 3;
|
|
unsigned int AIS : 1;
|
|
unsigned int L4F : 1;
|
|
unsigned int IPF : 1;
|
|
unsigned int L4FVLD_bit : 1;
|
|
unsigned int IPFVLD_bit : 1;
|
|
#endif
|
|
} bits;
|
|
uint32 word;
|
|
} PDMA_RXD_INFO4_T;
|
|
|
|
struct PDMA_rxdesc {
|
|
PDMA_RXD_INFO1_T rxd_info1;
|
|
PDMA_RXD_INFO2_T rxd_info2;
|
|
PDMA_RXD_INFO3_T rxd_info3;
|
|
PDMA_RXD_INFO4_T rxd_info4;
|
|
};
|
|
|
|
typedef struct PDMA_rxdesc macRxDescr_t;
|
|
|
|
/*=========================================
|
|
PDMA TX Descriptor Format define
|
|
=========================================*/
|
|
//-------------------------------------------------
|
|
|
|
typedef union {
|
|
struct _PDMA_TXD_INFO1_
|
|
{
|
|
unsigned int SDP0;
|
|
} bits;
|
|
uint32 word;
|
|
} PDMA_TXD_INFO1_T;
|
|
//-------------------------------------------------
|
|
|
|
typedef union {
|
|
struct _PDMA_TXD_INFO2_
|
|
{
|
|
#ifdef __BIG_ENDIAN
|
|
unsigned int DDONE_bit : 1;
|
|
unsigned int LS0_bit : 1;
|
|
unsigned int SDL0 : 14;
|
|
unsigned int BURST_bit : 1;
|
|
unsigned int LS1_bit : 1;
|
|
unsigned int SDL1 : 14;
|
|
#else
|
|
unsigned int SDL1 : 14;
|
|
unsigned int LS1_bit : 1;
|
|
unsigned int BURST_bit : 1;
|
|
unsigned int SDL0 : 14;
|
|
unsigned int LS0_bit : 1;
|
|
unsigned int DDONE_bit : 1;
|
|
#endif
|
|
} bits;
|
|
uint32 word;
|
|
} PDMA_TXD_INFO2_T;
|
|
//-------------------------------------------------
|
|
|
|
typedef union {
|
|
struct _PDMA_TXD_INFO3_
|
|
{
|
|
unsigned int SDP1;
|
|
} bits;
|
|
uint32 word;
|
|
} PDMA_TXD_INFO3_T;
|
|
//-------------------------------------------------
|
|
|
|
typedef union {
|
|
struct _PDMA_TXD_INFO4_
|
|
{
|
|
#ifdef __BIG_ENDIAN
|
|
unsigned int ICO : 1;
|
|
unsigned int UCO : 1;
|
|
unsigned int TCO : 1;
|
|
unsigned int UN_USE1 : 2;
|
|
unsigned int PN : 3;
|
|
unsigned int UDF : 4;
|
|
unsigned int UN_USE2 : 1;
|
|
unsigned int QN : 3;
|
|
unsigned int UN_USE3 : 2;
|
|
unsigned int RESV : 1;
|
|
unsigned int INSP : 1;
|
|
unsigned int SIDX : 4;
|
|
unsigned int INSV : 1;
|
|
unsigned int VPRI : 3;
|
|
unsigned int VIDX : 4;
|
|
#else
|
|
unsigned int VIDX : 4;
|
|
unsigned int VPRI : 3;
|
|
unsigned int INSV : 1;
|
|
unsigned int SIDX : 4;
|
|
unsigned int INSP : 1;
|
|
unsigned int RESV : 1;
|
|
unsigned int UN_USE3 : 2;
|
|
unsigned int QN : 3;
|
|
unsigned int UN_USE2 : 1;
|
|
unsigned int UDF : 4;
|
|
unsigned int PN : 3;
|
|
unsigned int UN_USE1 : 2;
|
|
unsigned int TCO : 1;
|
|
unsigned int UCO : 1;
|
|
unsigned int ICO : 1;
|
|
#endif
|
|
} bits;
|
|
uint32 word;
|
|
} PDMA_TXD_INFO4_T;
|
|
|
|
struct PDMA_txdesc {
|
|
PDMA_TXD_INFO1_T txd_info1;
|
|
PDMA_TXD_INFO2_T txd_info2;
|
|
PDMA_TXD_INFO3_T txd_info3;
|
|
PDMA_TXD_INFO4_T txd_info4;
|
|
};
|
|
|
|
typedef struct PDMA_txdesc macTxDescr_t;
|
|
|
|
/*********************
|
|
* Mac Control Block *
|
|
*********************/
|
|
|
|
typedef struct macDrvCtrl_s
|
|
{
|
|
macTxDescr_t *txFreeDescr_p; /* Tx free descriptor */
|
|
|
|
macTxDescr_t *txBusyDescr_p; /* Tx busy descriptor */
|
|
uint16 txQueuedFrameCnt; /* cnts of frames haven't freed yet */
|
|
uint32 macDrvResetCnt; /* reset counts */
|
|
} macDrvCtrl_t;
|
|
|
|
|
|
/* ----- MIB-II ----- */
|
|
typedef struct macMIB_II_s
|
|
{
|
|
uint32 ifadminstatus; /* MIB adminstatus */
|
|
uint32 inOctets; /* Receive Octets */
|
|
uint32 inUnicastPkts; /* Receive Unicast Packets */
|
|
uint32 inMulticastPkts; /* Receive Multicast Packets */
|
|
uint32 inDiscards; /* Receive Discard Packets */
|
|
uint32 inErrors; /* Receive Error Packets */
|
|
uint32 inUnknownProtocols; /* Receive Unknown Prototol Packets */
|
|
uint32 outOctets; /* Transmit Octets */
|
|
uint32 outUnicastPkts; /* Transmit Unicast Packets */
|
|
uint32 outMulticastPkts; /* Transmit Multicast Packets */
|
|
uint32 outDiscards; /* Transmit Discard Packets */
|
|
uint32 outErrors; /* Transmit Error Packets */
|
|
} macMIB_II_t;
|
|
|
|
/* ----- Adapter Statistics ----- */
|
|
typedef struct inSiliconStat_s {
|
|
uint32 txJabberTimeCnt;
|
|
uint32 txLossOfCarrierCnt;
|
|
uint32 txNoCarrierCnt;
|
|
uint32 txLateCollisionCnt;
|
|
uint32 txExCollisionCnt;
|
|
uint32 txHeartbeatFailCnt;
|
|
uint32 txCollisionCnt;
|
|
uint32 txExDeferralCnt;
|
|
uint32 txUnderRunCnt;
|
|
|
|
uint32 rxAlignErr;
|
|
uint32 rxSymbolErr;
|
|
uint32 rxMiiErr;
|
|
uint32 rxCrcErr;
|
|
uint32 rxEtherFrameLengthErr; /* 60 > size(Packet) or 1518 < size(Packet) */
|
|
uint32 rx802p3FrameLengthErr; /* value of length field of 802.3 packet is
|
|
larger than real packet payload */
|
|
uint32 rxDribblingErr;
|
|
uint32 rxRuntErr;
|
|
uint32 rxLongErr;
|
|
uint32 rxCollisionErr;
|
|
|
|
uint32 rxPktIPChkSumErr;
|
|
|
|
uint32 rxEnQueueNum; /* Number of packets enqueued in macRxRingproc() */
|
|
uint32 rxDeQueueNum; /* Number of packets dequeued in macRxToUpperTask() */
|
|
uint32 txEnQueueNum; /* Number of packets enqueued in macSend() */
|
|
uint32 txDeQueueNum; /* Number of packets dequeued in macTxRingproc() */
|
|
|
|
} inSiliconStat_t;
|
|
|
|
|
|
/* ----- Ethernet Link Profile ----- */
|
|
typedef struct macPhyLinkProfile_s
|
|
{
|
|
uint32 linkSpeed; /* 10Mbps or 100Mbps */
|
|
uint32 duplexMode; /* Half/Full Duplex Mode */
|
|
uint32 enetMode;
|
|
uint32 ANCompFlag; /* auto_negotiation complete Flag */
|
|
uint32 PollCount; /* auto_negotiation polling check count */
|
|
} macPhyLinkProfile_t;
|
|
|
|
/* with 16 byte alignment */
|
|
#define DESCRIPTOR_POOL_SIZE ( MAC_RXDESCP_SIZE*MAC_RXDESCP_NO + 8*MAC_TXDESCP_SIZE*MAC_TXDESCP_NO + 32 )
|
|
|
|
/* ----- Ethernet private memory pool ----- */
|
|
typedef struct macMemPool_s
|
|
{
|
|
uint8 descrPool[DESCRIPTOR_POOL_SIZE]; /* Descr pool area */
|
|
} macMemPool_t;
|
|
|
|
/* ----- Ethernet memory allocation map ----- */
|
|
typedef struct macAllocMap_s
|
|
{
|
|
uint32 txDescpBaseVA; /* tx descriptor base virtual address */
|
|
uint32 rxDescpBaseVA; /* rx descriptor base virtual address */
|
|
} macAllocMap_t;
|
|
|
|
/* ----- Statistics for TC35815 ----- */
|
|
typedef struct macStat_s
|
|
{
|
|
macMIB_II_t MIB_II; /* MIB-II */
|
|
inSiliconStat_t inSilicon; /* TC35815 statistics */
|
|
|
|
} macStat_t;
|
|
|
|
/* ----- Adapter Card Table ------ */
|
|
typedef struct macAdapter_s
|
|
{
|
|
uint32 ChanID; /* Channel ID */
|
|
//uint32 slotNumber; /* PCI Slot No.(Indx No.) */
|
|
uint8 macAddr[6]; /* MAC-Address */
|
|
|
|
macPhyLinkProfile_t *macPhyLinkProfile_p;
|
|
//macAllocMap_t *macAllocMap_p;
|
|
macMemPool_t *macMemPool_p;
|
|
macStat_t *macStat_p;
|
|
uint8 statisticOn; /* Flag to record statistics or not */
|
|
|
|
//uint32 ioBaseAddr; /* PCI I/O Base Address */
|
|
|
|
uint32 descrSize; /* Reserved */
|
|
uint32 rxRingSize; /* Receive Descr Ring Size */
|
|
#if 0 //050913 bread move these three new entries to be compatible with old definition
|
|
uint32 txRingSize; /* Receive Descr Ring Size */
|
|
uint32 rxDescrSize; /* The size of a Rx descr entry in the descr ring */
|
|
uint32 txDescrSize; /* The size of a Tx descr entry in the descr ring */
|
|
#endif
|
|
uint32 resetNum; /* Number of Reset the LAN Cont. */
|
|
uint32 enetPhyAddr;
|
|
uint8 enetPhyId;
|
|
|
|
/* zd2001 */
|
|
macTxDescr_t* txCurrDescp; /* Currently working tx descriptor */
|
|
uint32 txDescrRingBaseVAddr; /* Transmit Descr Ring Virtual Address with 4byte alignment */
|
|
uint32 rxDescrRingBaseVAddr; /* Receive Descr Ring Virtual Address with 4byte alignment*/
|
|
uint32 txCurrentDescp; /* index to current tx descriptor */
|
|
uint32 txUnReleasedDescp; /* index to the unreleased descp of Tx */
|
|
uint32 txUnReleasedBufCnt; /* Unreleased buffer cnt hold by Tx */
|
|
uint32 rxCurrentDescp; /* index to current rx descriptor */
|
|
|
|
//050913 bread moved here
|
|
uint32 txRingSize; /* Receive Descr Ring Size */
|
|
uint32 rxDescrSize; /* The size of a Rx descr entry in the descr ring */
|
|
uint32 txDescrSize; /* The size of a Tx descr entry in the descr ring */
|
|
////
|
|
sk_buff *txskbs[MAC_TXDESCP_NO];
|
|
sk_buff *rxskbs[MAC_RXDESCP_NO];
|
|
} macAdapter_t;
|
|
|
|
typedef struct phyDeviceList_s {
|
|
uint16 companyId;
|
|
char vendorName[30];
|
|
} phyDeviceList_t;
|
|
|
|
int tc3162_eth_init(unsigned char *mac_addr);
|
|
int tc3162_eth_send(sk_buff *skb);
|
|
|
|
int tc3162_eth_exit(void);
|
|
|
|
#endif /* _FEMAC_H */
|
|
|