839 lines
30 KiB
C
Executable File
839 lines
30 KiB
C
Executable File
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#include "skbuff.h"
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/* ----- PHY-Chip Definition ----- */
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#define PHY_WRITE 0x0400
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#define PHY_BUSY 0x0800
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#define PHY_CONTROL_REG 0 /* MII Control Register */
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#define PHY_RESET 0x8000
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#define PHY_POWER_DOWN 0x0800
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#define PHY_AN_ENABLE 0x1000
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#define PHY_RESTART_AN 0x200
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#define PHY_SPEED_SELECT_100 0x2000
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#define PHY_FULL_DUPLEX 0x100
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#define PHY_ISOLATE 0x400
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#define PHY_LOOPBACK 0x4000
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#define PHY_STATUS_REG 1 /* MII Status Register */
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#define PHY_AN_COMPLETE 0x0020
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#define PHY_LINK_STATUS 0x0004
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#define PHY_ID_REG1 2 /* Identifier register 1 */
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#define PHY_ID_REG2 3 /* Identifier register 2 */
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#define PHY_REMOTE_CAP_REG 5 /* Auto-Negotiation Link Partner Ability Reg */
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#define PHY_100_BASE_T4 0x200
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#define PHY_100_BASE_TX_FD 0x100
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#define PHY_100_BASE_TX_HD 0x80
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#define PHY_10_BASE_T_FD 0x40
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#define PHY_10_BASE_T_HD 0x20
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#define PHY_CONFIG_REG 16
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#define PHY_TP_LOOPBACK 0x0100
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/* ----- 100/10Mbps Mode ----- */
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//#define AUTO_SENSE 0
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//#define TEN_MBPS 100000
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//#define ONE_HUNDRED_MBPS 1000000
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#define MIIDR_RESTART_AUTO_NEGOTIATE 0x0200
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#define MIIDR_ENABLE_AUTO_NEGOTIATE 0x1000
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#define MIIDR_10MBps 0x0000
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#define MIIDR_100MBps 0x2000
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#define MIIDR_AUTO_NEGOTIATE ( MIIDR_RESTART_AUTO_NEGOTIATE| MIIDR_ENABLE_AUTO_NEGOTIATE )
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#define MIIDR_FULL_DUPLEX 0x0100
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#define MIIDR_HALF_DUPLEX 0x0000
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#define MIIAR_WRITE 0x2
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#define MIIAR_READ 0x0
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#define MIIAR_IS_BUSY 0x1
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#define LINK_SPEED AUTO_SENSE
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#define CONFIG_QDMA_CHANNEL 8
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#define CONFIG_QDMA_QUEUE 8
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#define CONFIG_HWFWD_DSCP_NUM (4) //shoule not more than 4096
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#define CONFIG_HWFWD_DSCP_SIZE (16) //shoule not more than 4096
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#define CONFIG_MAX_PKT_LENS (2048)
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#define CONFIG_DSCP_NUM_MAX (4096)
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#define CONFIG_IRQ_NUM_MAX (4095)
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#define CONFIG_TX0_DSCP_NUM (16)
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#define CONFIG_RX0_DSCP_NUM (16)
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#define CONFIG_TX0_DSCP_SIZE (32) //4 //4desc + 4msg
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#define CONFIG_RX0_DSCP_SIZE (32) //4desc + 4msg
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#define CONFIG_IRQ_DEPTH (32)
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#define CONFIG_MAX_PKT_LENS (2048)
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#define HWFWD_LOW_THRESHOLD (1)
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#define QDMA_RX_DSCP_MSG_LENS (16)
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#define QDMA_TX_DSCP_MSG_LENS (8)
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#define QDMA_TX_THRESHOLD (4)
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#define DESC_INFONODE_SIZE (16)
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#define DESC_INFO_SIZE ((CONFIG_TX0_DSCP_NUM + CONFIG_RX0_DSCP_NUM)*DESC_INFONODE_SIZE)
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#define DESC_TOTAL_SIZE (CONFIG_TX0_DSCP_NUM*CONFIG_TX0_DSCP_SIZE + CONFIG_RX0_DSCP_NUM*CONFIG_RX0_DSCP_SIZE)
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#define HWFWD_TOTAL_SIZE (CONFIG_MAX_PKT_LENS + CONFIG_HWFWD_DSCP_SIZE)* CONFIG_HWFWD_DSCP_NUM
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#define MEM_POOL_SIZE (DESC_TOTAL_SIZE + (CONFIG_IRQ_DEPTH<<2) + HWFWD_TOTAL_SIZE)
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#define RING_IDX_0 0
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#define QDMA_ENABLE 1
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#define QDMA_DISABLE 0
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#define CONFIG_IRQ_DEF_VALUE (0xFFFFFFFF)
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#define read_reg_word(reg) VPint(reg)
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#define write_reg_word(reg, wdata) VPint(reg)=wdata
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#define printf prom_printf
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#define wmb() __asm__ __volatile("sync");
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#define K0_TO_K1(x) (((uint32)x) | 0xa0000000)
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#define K1_TO_PHY(x) (((uint32)x) & 0x1fffffff)
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#define IO_GREG(reg) read_reg_word((reg))
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#define IO_SREG(reg, value) write_reg_word((reg), value)
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#define IO_GMASK(reg, mask, shift) ((read_reg_word((reg)) & mask) >> shift)
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#define IO_SMASK(reg, mask, shift, value) { uint t = read_reg_word((reg)); write_reg_word((reg), ((t&~(mask))|((value<<shift)&mask))); }
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#define IO_SBITS(reg, bit) { uint t = read_reg_word((reg)); write_reg_word((reg), (t|bit)); }
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#ifdef CONFIG_DEBUG
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#define QDMA_MSG(level, F, B...) { \
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if(gpQdmaPriv->dbgLevel >= level) \
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printf("%s [%d]: " F, strrchr(__FILE__, '/')+1, __LINE__, ##B) ; \
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}
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#define QDMA_ERR(F, B...) printf("%s [%d]: " F, strrchr(__FILE__, '/')+1, __LINE__, ##B)
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#define QDMA_LOG(F, B...) printf("%s [%d]: " F, strrchr(__FILE__, '/')+1, __LINE__, ##B)
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#else
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#define QDMA_MSG(level, F, B...)
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#define QDMA_ERR(F,B...) printf(F, ##B) ;
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#define QDMA_LOG(F,B...) printf(F, ##B) ;
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#endif
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typedef struct {
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uint pkt_addr ;
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struct {
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#ifdef __BIG_ENDIAN
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uint ctx : 1 ;
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uint resv : 2 ;
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uint ctx_ring : 1 ;
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uint ctx_idx : 12 ;
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uint pkt_len : 16 ;
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#else
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uint pkt_len : 16 ;
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uint ctx_idx : 12 ;
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uint ctx_ring : 1 ;
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uint resv : 2 ;
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uint ctx : 1 ;
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#endif /* __BIG_ENDIAN */
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} ctrl ;
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uint msg[2] ;
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} QDMA_HWFWD_DMA_DSCP_T ;
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typedef struct {
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ushort IrqQueueAsynchronous ;
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ushort txIrqQueueIdxErrs ;
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uint txCounts ;
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uint txRecycleCounts ;
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uint txQdmaDropCounts ;
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uint rxCounts ;
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ushort txDscpIncorrect ;
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ushort rxDscpIncorrect ;
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ushort rxPktErrs ;
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ushort noTxDscps ;
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ushort noRxDscps ;
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} BM_Counters_T ;
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typedef union {
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struct {
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#ifdef __BIG_ENDIAN
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uint32 resv1 : 1;
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uint32 tsid : 5;
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uint32 tse : 1;
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uint32 dei : 1;
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uint32 resv2 : 12;
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uint32 oam : 1;
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uint32 channel : 8;
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uint32 queue : 3;
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#else
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uint32 queue : 3;
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uint32 channel : 8;
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uint32 oam : 1;
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uint32 resv2 : 12;
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uint32 dei : 1;
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uint32 tse : 1;
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uint32 tsid : 5;
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uint32 resv1 : 1;
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#endif /* __BIG_ENDIAN */
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#ifdef __BIG_ENDIAN
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uint32 ico : 1;
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uint32 uco : 1;
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uint32 tco : 1;
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uint32 tso : 1;
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uint32 resv3 : 6;
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uint32 fPort : 3;
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uint32 vlanEn : 1;
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uint32 vlanTpID : 2;
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uint32 vlanTag : 16;
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#else
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uint32 vlanTag : 16;
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uint32 vlanTpID : 2;
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uint32 vlanEn : 1;
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uint32 fPort : 3;
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uint32 resv3 : 6;
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uint32 tso : 1;
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uint32 tco : 1;
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uint32 uco : 1;
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uint32 ico : 1;
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#endif /* __BIG_ENDIAN */
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} raw ;
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uint msg[2] ;
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} ethTxMsg_t ;
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typedef union
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{
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uint32 word;
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} rxMsgWord0_t;
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typedef union
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{
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uint32 word;
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} rxMsgWord1_t;
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typedef union
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{
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uint32 word;
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} rxMsgWord2_t;
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typedef struct ethRxMsg_s
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{
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rxMsgWord0_t rxMsgW0;
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rxMsgWord1_t rxMsgW1;
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rxMsgWord2_t rxMsgW2;
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uint32 resv;
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} ethRxMsg_t;
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typedef struct {
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uint resv1 ;
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struct {
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#ifdef __BIG_ENDIAN
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uint done : 1 ;
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uint drop_pkt : 1 ;
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uint resv2 : 14 ;
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uint pkt_len : 16 ;
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#else
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uint pkt_len : 16 ;
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uint resv2 : 14 ;
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uint drop_pkt : 1 ;
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uint done : 1 ;
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#endif /* __BIG_ENDIAN */
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} ctrl ;
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uint pkt_addr ;
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#ifdef __BIG_ENDIAN
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uint resv3 : 20 ;
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uint next_idx : 12 ;
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#else
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uint next_idx : 12 ;
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uint resv3 : 20 ;
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#endif /* __BIG_ENDIAN */
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uint msg[4] ;
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} QDMA_DMA_DSCP_T ;
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struct QDMA_DscpInfo_S {
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QDMA_DMA_DSCP_T *dscpPtr ;
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uint dscpIdx ;
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sk_buff *skb ;
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struct QDMA_DscpInfo_S *next ;
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} ;
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typedef struct {
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uint csrBaseAddr ;
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ushort txDscpNum ; /* Total TX DSCP number */
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ushort rxDscpNum ; /* Total RX DSCP number */
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ushort hwFwdDscpNum ;
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ushort irqDepth ; /* Max depth for IRQ queue */
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ushort hwPktSize ;
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uint dscpInfoAddr ; /* Start pointer for DSCP information node */
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uint txBaseAddr ;
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uint rxBaseAddr ;
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uint irqQueueAddr ; /* IRQ queue address */
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uint hwFwdBaseAddr ; /* Base address of the hardware forwarding */
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uint hwFwdBuffAddr ; /* Base address of the hardware forwarding Buffer*/
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uint hwFwdPayloadSize ; /* Payload size of the hardware forwarding Buffer*/
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struct QDMA_DscpInfo_S *txHeadPtr ; /* Head node for unused tx desc. */
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struct QDMA_DscpInfo_S *txTailPtr ; /* Tail node for unused tx desc. */
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struct QDMA_DscpInfo_S *txUsingPtr ; /* TXDMA using DSCP node. */
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struct QDMA_DscpInfo_S *rxStartPtr ; /* Start using node for rx desc. */
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struct QDMA_DscpInfo_S *rxEndPtr ; /* End using node for rx desc. */
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struct QDMA_DscpInfo_S *rxUsingPtr ; /* RXDMA using DSCP node. */
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BM_Counters_T counters ;
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} QDMA_Private_T ;
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typedef struct macMemPool_s
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{
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uint8 descrPool[MEM_POOL_SIZE]; /* Descr pool area */
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} macMemPool_t;
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/* ----- Ethernet Link Profile ----- */
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typedef struct macPhyLinkProfile_s {
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uint32 linkSpeed; /* 10Mbps or 100Mbps */
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uint32 duplexMode; /* Half/Full Duplex Mode */
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uint32 enetMode;
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uint32 ANCompFlag; /* auto_negotiation complete Flag */
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uint32 PollCount; /* auto_negotiation polling check count */
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} macPhyLinkProfile_t;
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typedef struct macAdapter_s
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{
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uint8 macAddr[6]; /* MAC-Address */
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macPhyLinkProfile_t *macPhyLinkProfile_p;
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macMemPool_t *macMemPool_p;
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uint32 enetPhyAddr;
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uint8 enetPhyId;
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} macAdapter_t;
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typedef struct phyDeviceList_s {
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uint16 companyId;
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char vendorName[30];
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} phyDeviceList_t;
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#define GDMA1_BASE (0xBFB50500)
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#define GDMA1_FWD_CFG (GDMA1_BASE + 0x00)
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#define GDMA1_SHRP_CFG (GDMA1_BASE + 0x04)
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#define GDMA1_MAC_ADRL (GDMA1_BASE + 0x08)
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#define GDMA1_MAC_ADRH (GDMA1_BASE + 0x0c)
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#define GDMA1_VLAN_GEN (GDMA1_BASE + 0x10)
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#define GDMA1_LEN_CFG (GDMA1_BASE + 0x14)
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#define CONFIG_QDMA_BASE_ADDR (0x1FB54000)
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#define QDMA_REG_BASE (0xBFB54000)
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#define RING_OFFSET(idx) (idx<<8)
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/*******************************************************
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CSR for QDMA
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********************************************************/
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#define QDMA_CSR_INFO(base) (base+0x0000)
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#define QDMA_CSR_GLB_CFG(base) (base+0x0004)
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#define QDMA_CSR_TX_DSCP_BASE(base, idx) (base+0x0008+RING_OFFSET(idx))
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#define QDMA_CSR_RX_DSCP_BASE(base, idx) (base+0x000C+RING_OFFSET(idx))
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#define QDMA_CSR_TX_CPU_IDX(base, idx) (base+0x0010+RING_OFFSET(idx))
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#define QDMA_CSR_TX_DMA_IDX(base, idx) (base+0x0014+RING_OFFSET(idx))
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#define QDMA_CSR_RX_CPU_IDX(base, idx) (base+0x0018+RING_OFFSET(idx))
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#define QDMA_CSR_RX_DMA_IDX(base, idx) (base+0x001C+RING_OFFSET(idx))
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#define QDMA_CSR_HWFWD_DSCP_BASE(base) (base+0x0020)
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#define QDMA_CSR_HWFWD_BUFF_BASE(base) (base+0x0024)
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#define QDMA_CSR_HWFWD_DSCP_CFG(base) (base+0x0028)
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#define QDMA_CSR_LMGR_INIT_CFG(base) (base+0x0030)
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#define QDMA_CSR_LMGR_CHNL_RETIRE(base) (base+0x0040)
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#define QDMA_CSR_INT_STATUS(base) (base+0x0050)
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#define QDMA_CSR_INT_ENABLE(base) (base+0x0054)
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#define QDMA_CSR_TX_DELAY_INT_CFG(base) (base+0x0058)
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#define QDMA_CSR_RX_DELAY_INT_CFG(base) (base+0x005C)
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#define QDMA_CSR_IRQ_BASE(base) (base+0x0060)
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#define QDMA_CSR_IRQ_CFG(base) (base+0x0064)
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#define QDMA_CSR_IRQ_CLEAR_LEN(base) (base+0x0068)
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#define QDMA_CSR_IRQ_STATUS(base) (base+0x006C)
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#define QDMA_CSR_IRQ_PTIME(base) (base+0x0070)
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#define QDMA_CSR_TXWRR_MODE_CFG(base) (base+0x0080)
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#define QDMA_CSR_TXWRR_WEIGHT_CFG(base) (base+0x0088)
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#define QDMA_CSR_PSE_BUF_USAGE_CFG(base) (base+0x0090)
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#define QDMA_CSR_EGRESS_RATEMETER_CFG(base) (base+0x0094)
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#define QDMA_CSR_EGRESS_RATELIMIT_CFG(base) (base+0x0098)
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#define QDMA_CSR_RATELIMIT_PARAMETER_CFG(base) (base+0x009C)
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#define QDMA_CSR_TXQ_CNGST_CFG(base) (base+0x00A0)
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#define QDMA_CSR_TXQ_CNGST_TOTALTHR(base) (base+0x00A4)
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#define QDMA_CSR_TXQ_DYN_CHNLTHR_CFG(base) (base+0x00A8)
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#define QDMA_CSR_TXQ_DYN_QUEUETHR_CFG(base) (base+0x00AC)
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#define QDMA_CSR_STATIC_QUEUE_THR(base, i) (base+0x00B0+(i<<2))
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#define QDMA_CSR_DBG_LMGR_STATUS(base) (base+0x00F0)
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#define QDMA_CSR_DBG_QDMA_PROBE_LO(base) (base+0x00F8)
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#define QDMA_CSR_DBG_QDMA_PROBE_HI(base) (base+0x00FC)
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#define QDMA_CSR_RX_RING_CFG(base) (base+0x0100)
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#define QDMA_CSR_RX_RING_THR(base) (base+0x0104)
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#define QDMA_CSR_PERCHNL_QOS_MODE(base, i) (base+0x0180+(i<<2))
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#define QDMA_CSR_PERCHNL_DATARATE(base, i) (base+0x0200+(i<<2))
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#define QDMA_CSR_DBG_CNTR_CFG(base, i) (base+0x0300+(i<<3))
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#define QDMA_CSR_DBG_CNTR_VAR(base, i) (base+0x0304+(i<<3))
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#define QDMA_CSR_INT_STATUS(base) (base+0x0050)
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#define QDMA_CSR_INT_ENABLE(base) (base+0x0054)
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#define qdmaSetTxDscpBase(base, idx, val) IO_SREG(QDMA_CSR_TX_DSCP_BASE(base, idx), val)
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#define qdmaGetTxDscpBase(base, idx) IO_GREG(QDMA_CSR_TX_DSCP_BASE(base, idx))
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#define qdmaSetRxDscpBase(base, idx, val) IO_SREG(QDMA_CSR_RX_DSCP_BASE(base, idx), val)
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#define qdmaGetRxDscpBase(base, idx) IO_GREG(QDMA_CSR_RX_DSCP_BASE(base, idx))
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#define qdmaSetTxCpuIdx(base, idx, val) IO_SMASK(QDMA_CSR_TX_CPU_IDX(base, idx), TX_CPU_IDX_MASK, TX_CPU_IDX_SHIFT, val)
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#define qdmaGetTxCpuIdx(base, idx) IO_GMASK(QDMA_CSR_TX_CPU_IDX(base, idx), TX_CPU_IDX_MASK, TX_CPU_IDX_SHIFT)
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#define qdmaSetTxDmaIdx(base, idx, val) IO_SMASK(QDMA_CSR_TX_DMA_IDX(base, idx), TX_DMA_IDX_MASK, TX_DMA_IDX_SHIFT, val)
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#define qdmaGetTxDmaIdx(base, idx) IO_GMASK(QDMA_CSR_TX_DMA_IDX(base, idx), TX_DMA_IDX_MASK, TX_DMA_IDX_SHIFT)
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#define qdmaSetRxCpuIdx(base, idx, val) IO_SMASK(QDMA_CSR_RX_CPU_IDX(base, idx), RX_CPU_IDX_MASK, RX_CPU_IDX_SHIFT, val)
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#define qdmaGetRxCpuIdx(base, idx) IO_GMASK(QDMA_CSR_RX_CPU_IDX(base, idx), RX_CPU_IDX_MASK, RX_CPU_IDX_SHIFT)
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#define qdmaSetRxDmaIdx(base, idx, val) IO_SMASK(QDMA_CSR_RX_DMA_IDX(base, idx), RX_DMA_IDX_MASK, RX_DMA_IDX_SHIFT, val)
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#define qdmaGetRxDmaIdx(base, idx) IO_GMASK(QDMA_CSR_RX_DMA_IDX(base, idx), RX_DMA_IDX_MASK, RX_DMA_IDX_SHIFT)
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#define qdmaSetRxRingSize(base, idx, val) IO_SMASK(QDMA_CSR_RX_RING_CFG(base), RX_RING_SIZE_MASK(idx), RX_RING_SIZE_SHIFT(idx), val)
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#define qdmaGetRxRingSize(base, idx) IO_GMASK(QDMA_CSR_RX_RING_CFG(base), RX_RING_SIZE_MASK(idx), RX_RING_SIZE_SHIFT(idx))
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#define qdmaSetRxRingThrh(base, idx, val) IO_SMASK(QDMA_CSR_RX_RING_THR(base), RX_RING_LOW_THR_MASK(idx), RX_RING_LOW_THR_SHIFT(idx), val)
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#define qdmaGetRxRingThrh(base, idx) IO_GMASK(QDMA_CSR_RX_RING_THR(base), RX_RING_LOW_THR_MASK(idx), RX_RING_LOW_THR_SHIFT(idx))
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#define qdmaSetHwDscpBase(base, val) IO_SREG(QDMA_CSR_HWFWD_DSCP_BASE(base), val)
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#define qdmaGetHwDscpBase(base) IO_GREG(QDMA_CSR_HWFWD_DSCP_BASE(base))
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#define qdmaSetHwBuffBase(base, val) IO_SREG(QDMA_CSR_HWFWD_BUFF_BASE(base), val)
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#define qdmaGetHwBuffBase(base) IO_GREG(QDMA_CSR_HWFWD_BUFF_BASE(base))
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#define qdmaSetHwPayloadSize(base, val) IO_SMASK(QDMA_CSR_HWFWD_DSCP_CFG(base), HWFWD_PAYLOAD_SIZE_MASK, HWFWD_PAYLOAD_SIZE_SHIFT, val)
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#define qdmaGetHwPayloadSize(base) IO_GMASK(QDMA_CSR_HWFWD_DSCP_CFG(base), HWFWD_PAYLOAD_SIZE_MASK, HWFWD_PAYLOAD_SIZE_SHIFT)
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#define qdmaSetHwLowThrshld(base, val) IO_SMASK(QDMA_CSR_HWFWD_DSCP_CFG(base), HWFWD_DSCP_LOW_THRSHLD_MASK, HWFWD_DSCP_LOW_THRSHLD_SHIFT, val)
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#define qdmaGetHwLowThrshld(base) IO_GMASK(QDMA_CSR_HWFWD_DSCP_CFG(base), HWFWD_DSCP_LOW_THRSHLD_MASK, HWFWD_DSCP_LOW_THRSHLD_SHIFT)
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#define qdmaSetHwDscpNum(base, val) IO_SMASK(QDMA_CSR_LMGR_INIT_CFG(base), HWFWD_DSCP_NUM_MASK, HWFWD_DSCP_NUM_SHIFT, val)
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#define qdmaGetHwDscpNum(base) IO_GMASK(QDMA_CSR_LMGR_INIT_CFG(base), HWFWD_DSCP_NUM_MASK, HWFWD_DSCP_NUM_SHIFT)
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#define qdmaSetHWInitStart(base) IO_SBITS(QDMA_CSR_LMGR_INIT_CFG(base), LMGR_INIT_START)
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#define qdmaGetHWInitStart(base) (IO_GREG(QDMA_CSR_LMGR_INIT_CFG(base)) & LMGR_INIT_START)
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#define qdmaSetGlbCfg(base, val) IO_SREG(QDMA_CSR_GLB_CFG(base), val)
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#define qdmaGetIntStatus(base) IO_GREG(QDMA_CSR_INT_STATUS(base))
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#define qdmaGetIrqEntryLen(base) IO_GMASK(QDMA_CSR_IRQ_STATUS(base), IRQ_STATUS_ENTRY_LEN_MASK, IRQ_STATUS_ENTRY_LEN_SHIFT)
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#define qdmaClearIntStatus(base, val) IO_SREG(QDMA_CSR_INT_STATUS(base), val)
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#define qdmaSetIntMask(base, val) IO_SREG(QDMA_CSR_INT_ENABLE(base), val)
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#define qdmaGetIrqStatus(base) IO_GREG(QDMA_CSR_IRQ_STATUS(base))
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#define qdmaGetIntMask(base) IO_GREG(QDMA_CSR_INT_ENABLE(base))
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#define qdmaSetIrqBase(base, val) IO_SREG(QDMA_CSR_IRQ_BASE(base), val)
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#define qdmaSetIrqDepth(base, val) IO_SMASK(QDMA_CSR_IRQ_CFG(base), IRQ_CFG_DEPTH_MASK, IRQ_CFG_DEPTH_SHIFT, val)
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#define qdmaSetIrqClearLen(base, val) IO_SMASK(QDMA_CSR_IRQ_CLEAR_LEN(base), IRQ_CLEAR_LEN_MASK, IRQ_CLEAR_LEN_SHIFT, val)
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#define qdmaEnableRxDma(base) IO_SBITS(QDMA_CSR_GLB_CFG(base), GLB_CFG_RX_DMA_EN)
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#define qdmaDisableRxDma(base) IO_CBITS(QDMA_CSR_GLB_CFG(base), GLB_CFG_RX_DMA_EN)
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#define qdmaEnableTxDma(base) IO_SBITS(QDMA_CSR_GLB_CFG(base), GLB_CFG_TX_DMA_EN)
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#define qdmaDisableTxDma(base) IO_CBITS(QDMA_CSR_GLB_CFG(base), GLB_CFG_TX_DMA_EN)
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/* define GDMA port */
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#define GDM_P_PDMA (0x0)
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#define GDM_P_GDMA1 (0x1)
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#define GDM_P_GDMA2 (0x2)
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#define GDM_P_PPE (0x4)
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#define GDM_P_QDMA (0x5)
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#define GDM_P_DISCARD (0x7)
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#define GDM_P_CPU GDM_P_PDMA
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/* QDMA_CSR_HWFWD_DSCP_CFG(base) */
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#define HWFWD_PAYLOAD_SIZE_SHIFT (28)
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#define HWFWD_PAYLOAD_SIZE_MASK (0x3<<HWFWD_PAYLOAD_SIZE_SHIFT)
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#define HWFWD_PAYLOAD_SIZE_2K (0x0)
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#define HWFWD_PAYLOAD_SIZE_4K (0x1)
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#define HWFWD_PAYLOAD_SIZE_8K (0x2)
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#define HWFWD_PAYLOAD_SIZE_16K (0x3)
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#define HWFWD_DSCP_LOW_THRSHLD_SHIFT (0)
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#define HWFWD_DSCP_LOW_THRSHLD_MASK (0x1FFF<<HWFWD_DSCP_LOW_THRSHLD_SHIFT)
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/* QDMA_CSR_INT_STATUS(base) */
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#define INT_STATUS_XPON_PHY (1<<24)
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#define INT_STATUS_EPON_MAC (1<<17)
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#define INT_STATUS_GPON_MAC (1<<16)
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#define INT_STATUS_RX1_COHERENT (1<<15)
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#define INT_STATUS_TX1_COHERENT (1<<14)
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#define INT_STATUS_RX0_COHERENT (1<<13)
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#define INT_STATUS_TX0_COHERENT (1<<12)
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#define INT_STATUS_HWFWD_DSCP_LOW (1<<10)
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#define INT_STATUS_IRQ_FULL (1<<9)
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#define INT_STATUS_HWFWD_DSCP_EMPTY (1<<8)
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#define INT_STATUS_NO_RX1_CPU_DSCP (1<<7)
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#define INT_STATUS_NO_TX1_CPU_DSCP (1<<6)
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#define INT_STATUS_RX1_DONE (1<<5)
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#define INT_STATUS_TX1_DONE (1<<4)
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#define INT_STATUS_NO_RX0_CPU_DSCP (1<<3)
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#define INT_STATUS_NO_TX0_CPU_DSCP (1<<2)
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#define INT_STATUS_RX0_DONE (1<<1)
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#define INT_STATUS_TX0_DONE (1<<0)
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#define INT_STATUS_QDMA_DONE (0x00000033)
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#define INT_STATUS_QDMA_FAULT (0x0000F740)
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#define INT_STATUS_EXTERNAL (0x01030000)
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/* QDMA_CSR_GLB_CFG(base) */
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#define GLB_CFG_RX_2B_OFFSET (1<<31)
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#define GLB_CFG_DMA_PREFERENCE_SHIFT (29)
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#define GLB_CFG_DMA_PREFERENCE_MASK (0x3<<GLB_CFG_DMA_PREFERENCE_SHIFT)
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#define PREFER_ROIND_ROBIN (0x00)
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#define PREFER_FWD_TX1_TX0 (0x01)
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#define PREFER_TX1_FWD_TX0 (0x10)
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#define PREFER_TX1_TX0_FWD (0x11)
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#define GLB_CFG_MSG_WORD_SWAP (1<<28)
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#define GLB_CFG_DSCP_BYTE_SWAP (1<<27)
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#define GLB_CFG_PAYLOAD_BYTE_SWAP (1<<26)
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#define GLB_CFG_SLM_RELEASE_EN (1<<21)
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#define GLB_CFG_TX_IMMEDIATE_DONE (1<<20)
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#define GLB_CFG_IRQ_EN (1<<19)
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#define GLB_CFG_LOOPCNT_EN (1<<18)
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#define GLB_CFG_UMAC_LOOPBACK (1<<17)
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#define GLB_CFG_QDMA_LOOPBACK (1<<16)
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#define GLB_CFG_CHECK_DONE (1<<7)
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#define GLB_CFG_TX_WB_DONE (1<<6)
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#define GLB_CFG_BST_SE_SHIFT (4)
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#define GLB_CFG_BST_SE_MASK (0x3<<GLB_CFG_BST_SE_SHIFT)
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#define VAL_BST_4_DWORD (0x0)
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#define VAL_BST_8_DWORD (0x1)
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#define VAL_BST_16_DWARD (0x2)
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#define VAL_BST_32_DWARD (0x3)
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#define GLB_CFG_RX_DMA_BUSY (1<<3)
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#define GLB_CFG_RX_DMA_EN (1<<2)
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#define GLB_CFG_TX_DMA_BUSY (1<<1)
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#define GLB_CFG_TX_DMA_EN (1<<0)
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/* QDMA_CSR_TX_CPU_IDX(base) */
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#define TX_CPU_IDX_SHIFT (0)
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#define TX_CPU_IDX_MASK (0xFFF<<TX_CPU_IDX_SHIFT)
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/* QDMA_CSR_TX_DMA_IDX(base) */
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#define TX_DMA_IDX_SHIFT (0)
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#define TX_DMA_IDX_MASK (0xFFF<<TX_DMA_IDX_SHIFT)
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/* QDMA_CSR_RX_CPU_IDX(base) */
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#define RX_CPU_IDX_SHIFT (0)
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#define RX_CPU_IDX_MASK (0xFFF<<RX_CPU_IDX_SHIFT)
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/* QDMA_CSR_RX_DMA_IDX(base) */
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#define RX_DMA_IDX_SHIFT (0)
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#define RX_DMA_IDX_MASK (0xFFF<<RX_DMA_IDX_SHIFT)
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/* QDMA_CSR_LMGR_INIT_CFG(base) */
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#define LMGR_INIT_START (1<<31)
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#define HWFWD_DSCP_NUM_SHIFT (0)
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#define HWFWD_DSCP_NUM_MASK (0x1FFF<<HWFWD_DSCP_NUM_SHIFT)
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/* QDMA_CSR_RX_RING_CFG */
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#define RX_RING_SIZE_SHIFT(idx) (idx<<4)
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#define RX_RING_SIZE_MASK(idx) (0xFFF<<RX_RING_SIZE_SHIFT(idx))
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/* QDMA_CSR_RX_RING_THR */
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#define RX_RING_LOW_THR_SHIFT(idx) (idx<<4)
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#define RX_RING_LOW_THR_MASK(idx) (0xFFF<<RX_RING_SIZE_SHIFT(idx))
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/* QDMA_CSR_IRQ_CFG(base) */
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#define IRQ_CFG_THRESHOLD_SHIFT (16)
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#define IRQ_CFG_THRESHOLD_MASK (0xFFF<<IRQ_CFG_THRESHOLD_SHIFT)
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#define IRQ_CFG_DEPTH_SHIFT (0)
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#define IRQ_CFG_DEPTH_MASK (0xFFF<<IRQ_CFG_DEPTH_SHIFT)
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/* QDMA_CSR_IRQ_CLEAR_LEN(base) */
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#define IRQ_CLEAR_LEN_SHIFT (0)
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#define IRQ_CLEAR_LEN_MASK (0xFF<<IRQ_CLEAR_LEN_SHIFT)
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/* GDMA1_FWD_CFG or GDMA2_FWD_CFG */
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#define GDM_JMB_LEN_SHIFT (28)
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#define GDM_JMB_LEN (0xf<<GDM_JMB_LEN_SHIFT)
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#define GDM_20US_TICK_SLT (1<<25)
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|
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#define GDM_INSV_EN (1<<26)
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#define GDM_UNTAG_EN (1<<25)
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#define GDM_STAG_EN (1<<24)
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#define GDM_ICS_EN (1<<22)
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#define GDM_TCS_EN (1<<21)
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#define GDM_UCS_EN (1<<20)
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#define GDM_DROP_256B (1<<19)
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#define GDM_DISPAD (1<<18)
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|
#define GDM_DISCRC (1<<17)
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|
#define GDM_STRPCRC (1<<16)
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#define GDM_UFRC_P_SHIFT (12)
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#define GDM_UFRC_P (0xf<<GDM_UFRC_P_SHIFT)
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#define GDM_BFRC_P_SHIFT (8)
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#define GDM_BFRC_P (0xf<<GDM_BFRC_P_SHIFT)
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#define GDM_MFRC_P_SHIFT (4)
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#define GDM_MFRC_P (0xf<<GDM_MFRC_P_SHIFT)
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#define GDM_OFRC_P_SHIFT (0)
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#define GDM_OFRC_P (0xf<<GDM_MFRC_P_SHIFT)
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/********************************
|
|
* Giga Switch Module Registers *
|
|
********************************/
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|
|
|
#define GSW_BASE 0xBFB58000
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|
#define GSW_ARL_BASE (GSW_BASE + 0x0000)
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#define GSW_BMU_BASE (GSW_BASE + 0x1000)
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#define GSW_PORT_BASE (GSW_BASE + 0x2000)
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#define GSW_MAC_BASE (GSW_BASE + 0x3000)
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#define GSW_MIB_BASE (GSW_BASE + 0x4000)
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#define GSW_CFG_BASE (GSW_BASE + 0x7000)
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|
|
|
|
#define GSW_ERLCR(n) (GSW_BASE + (n)*0x100 + 0x1040)
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|
|
|
#define GSW_MFC (GSW_ARL_BASE + 0x10)
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|
|
|
#define GSW_IMC (GSW_ARL_BASE + 0x1c)
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|
#define IMC_IGMP_RPT_FW_SHIFT (12)
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|
|
|
#define GSW_PSC(n) (GSW_PORT_BASE + (n)*0x100 + 0x0C)
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|
|
|
#define GSW_PMCR(n) (GSW_MAC_BASE + (n)*0x100)
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|
#define GSW_PMSR(n) (GSW_MAC_BASE + (n)*0x100 + 0x08)
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|
#define GSW_PINT_EN(n) (GSW_MAC_BASE + (n)*0x100 + 0x10)
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|
#define GSW_SMACCR0 (GSW_MAC_BASE + 0xe4)
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#define GSW_SMACCR1 (GSW_MAC_BASE + 0xe8)
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|
#define GSW_CKGCR (GSW_MAC_BASE + 0xf0)
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|
|
|
#define GSW_TX_DROC(n) (GSW_MIB_BASE + (n)*0x100 + 0x00)
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#define GSW_TX_CRC(n) (GSW_MIB_BASE + (n)*0x100 + 0x04)
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#define GSW_TX_UNIC(n) (GSW_MIB_BASE + (n)*0x100 + 0x08)
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#define GSW_TX_MULC(n) (GSW_MIB_BASE + (n)*0x100 + 0x0c)
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#define GSW_TX_BROC(n) (GSW_MIB_BASE + (n)*0x100 + 0x10)
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|
#define GSW_TX_COLC(n) (GSW_MIB_BASE + (n)*0x100 + 0x14)
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|
#define GSW_TX_SCOLC(n) (GSW_MIB_BASE + (n)*0x100 + 0x18)
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#define GSW_TX_MCOLC(n) (GSW_MIB_BASE + (n)*0x100 + 0x1c)
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#define GSW_TX_DEFC(n) (GSW_MIB_BASE + (n)*0x100 + 0x20)
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#define GSW_TX_LCOLC(n) (GSW_MIB_BASE + (n)*0x100 + 0x24)
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#define GSW_TX_ECOLC(n) (GSW_MIB_BASE + (n)*0x100 + 0x28)
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#define GSW_TX_PAUC(n) (GSW_MIB_BASE + (n)*0x100 + 0x2c)
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#define GSW_TX_OCL(n) (GSW_MIB_BASE + (n)*0x100 + 0x48)
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#define GSW_TX_OCH(n) (GSW_MIB_BASE + (n)*0x100 + 0x4c)
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|
|
|
#define GSW_RX_DROC(n) (GSW_MIB_BASE + (n)*0x100 + 0x60)
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|
#define GSW_RX_FILC(n) (GSW_MIB_BASE + (n)*0x100 + 0x64)
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#define GSW_RX_UNIC(n) (GSW_MIB_BASE + (n)*0x100 + 0x68)
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|
#define GSW_RX_MULC(n) (GSW_MIB_BASE + (n)*0x100 + 0x6c)
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|
#define GSW_RX_BROC(n) (GSW_MIB_BASE + (n)*0x100 + 0x70)
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|
#define GSW_RX_ALIGE(n) (GSW_MIB_BASE + (n)*0x100 + 0x74)
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#define GSW_RX_CRC(n) (GSW_MIB_BASE + (n)*0x100 + 0x78)
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#define GSW_RX_RUNT(n) (GSW_MIB_BASE + (n)*0x100 + 0x7c)
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|
#define GSW_RX_FRGE(n) (GSW_MIB_BASE + (n)*0x100 + 0x80)
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|
#define GSW_RX_LONG(n) (GSW_MIB_BASE + (n)*0x100 + 0x84)
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|
#define GSW_RX_JABE(n) (GSW_MIB_BASE + (n)*0x100 + 0x88)
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|
#define GSW_RX_PAUC(n) (GSW_MIB_BASE + (n)*0x100 + 0x8c)
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|
#define GSW_RX_OCL(n) (GSW_MIB_BASE + (n)*0x100 + 0xa8)
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|
#define GSW_RX_OCH(n) (GSW_MIB_BASE + (n)*0x100 + 0xac)
|
|
#define GSW_RX_INGC(n) (GSW_MIB_BASE + (n)*0x100 + 0xb4)
|
|
#define GSW_RX_ARLC(n) (GSW_MIB_BASE + (n)*0x100 + 0xb8)
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|
|
|
|
|
|
|
#define EXT_GSW_TX_DROC(n) (0x4000 + (n)*0x100)
|
|
#define EXT_GSW_TX_CRC(n) (0x4004 + (n)*0x100)
|
|
#define EXT_GSW_TX_UNIC(n) (0x4008 + (n)*0x100)
|
|
#define EXT_GSW_TX_MULC(n) (0x400c + (n)*0x100)
|
|
#define EXT_GSW_TX_BROC(n) (0x4010 + (n)*0x100)
|
|
#define EXT_GSW_TX_COLC(n) (0x4014 + (n)*0x100)
|
|
#define EXT_GSW_TX_SCOLC(n) (0x4018 + (n)*0x100)
|
|
#define EXT_GSW_TX_MCOLC(n) (0x401c + (n)*0x100)
|
|
#define EXT_GSW_TX_DEFC(n) (0x4020 + (n)*0x100)
|
|
#define EXT_GSW_TX_LCOLC(n) (0x4024 + (n)*0x100)
|
|
#define EXT_GSW_TX_ECOLC(n) (0x4028 + (n)*0x100)
|
|
#define EXT_GSW_TX_PAUC(n) (0x402c + (n)*0x100)
|
|
#define EXT_GSW_TX_OCL(n) (0x4048 + (n)*0x100)
|
|
#define EXT_GSW_TX_OCH(n) (0x404c + (n)*0x100)
|
|
|
|
#define EXT_GSW_RX_DROC(n) (0x4060 + (n)*0x100)
|
|
#define EXT_GSW_RX_FILC(n) (0x4064 + (n)*0x100)
|
|
#define EXT_GSW_RX_UNIC(n) (0x4068 + (n)*0x100)
|
|
#define EXT_GSW_RX_MULC(n) (0x406c + (n)*0x100)
|
|
#define EXT_GSW_RX_BROC(n) (0x4070 + (n)*0x100)
|
|
#define EXT_GSW_RX_ALIGE(n) (0x4074 + (n)*0x100)
|
|
#define EXT_GSW_RX_CRC(n) (0x4078 + (n)*0x100)
|
|
#define EXT_GSW_RX_RUNT(n) (0x407c + (n)*0x100)
|
|
#define EXT_GSW_RX_FRGE(n) (0x4080 + (n)*0x100)
|
|
#define EXT_GSW_RX_LONG(n) (0x4084 + (n)*0x100)
|
|
#define EXT_GSW_RX_JABE(n) (0x4088 + (n)*0x100)
|
|
#define EXT_GSW_RX_PAUC(n) (0x408c + (n)*0x100)
|
|
#define EXT_GSW_RX_OCL(n) (0x40a8 + (n)*0x100)
|
|
#define EXT_GSW_RX_OCH(n) (0x40ac + (n)*0x100)
|
|
#define EXT_GSW_RX_INGC(n) (0x40b4 + (n)*0x100)
|
|
#define EXT_GSW_RX_ARLC(n) (0x40b8 + (n)*0x100)
|
|
|
|
#define GSW_PVC(n) (0x2010 + (n)*0x100)
|
|
#define DEFAULT_TPID (0x8100)
|
|
|
|
#define GSW_CFG_PPSC (GSW_CFG_BASE + 0x18)
|
|
#define GSW_CFG_PIAC (GSW_CFG_BASE + 0x1c)
|
|
#define GSW_CFG_GPC (GSW_CFG_BASE + 0x14)
|
|
|
|
|
|
#define GSW_VLAN_REG (GSW_BASE+0x94)
|
|
#define GSW_ATA1_REG (GSW_BASE+0x74)
|
|
#define GSW_ATC_REG (GSW_BASE+0x80)
|
|
#define GSW_CFG_CREV (GSW_CFG_BASE + 0xFFC)
|
|
#define EXT_GSW_CFG_CREV (0x7FFC)
|
|
|
|
|
|
//switch define
|
|
/* GSW_MFC */
|
|
#define MFC_BC_FFP_SHIFT (24)
|
|
#define MFC_BC_FFP (0xff<<MFC_BC_FFP_SHIFT)
|
|
#define MFC_UNM_FFP_SHIFT (16)
|
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#define MFC_UNM_FFP (0xff<<MFC_UNM_FFP_SHIFT)
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#define MFC_UNU_FFP_SHIFT (8)
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#define MFC_UNU_FFP (0xff<<MFC_UNU_FFP_SHIFT)
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#define MFC_CPU_EN (1<<7)
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#define MFC_CPU_PORT_SHIFT (4)
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#define MFC_CPU_PORT (0x7<<MFC_CPU_PORT_SHIFT)
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#define MFC_MIRROR_EN (1<<3)
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#define MFC_MIRROR_PORT_SHIFT (0)
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#define MFC_MIRROT_PORT (0x7<<MFC_MIRROR_PORT_SHIFT)
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/* GSW_PMCR */
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#define IPG_CFG_PN_SHIFT (18)
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#define IPG_CFG_PN (0x3<<IPG_CFG_PN_SHIFT)
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#define EXT_PHY_PN (1<<17)
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#define MAC_MODE_PN (1<<16)
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#define FORCE_MODE_PN (1<<15)
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#define MAC_TX_EN_PN (1<<14)
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#define MAC_RX_EN_PN (1<<13)
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#define RGMII_MODE_PN (1<<12)
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#define BKOFF_EN_PN (1<<9)
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#define BACKPR_EN_PN (1<<8)
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#define ENABLE_EEE1G_PN (1<<7)
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#define ENABLE_EEE100_PN (1<<6)
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#define ENABLE_RX_FC_PN (1<<5)
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#define ENABLE_TX_FC_PN (1<<4)
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#define FORCE_SPD_PN_SHIFT (2)
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#define FORCE_SPD_PN (0x3<<FORCE_SPD_PN_SHIFT)
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#define FORCE_DPX_PN (1<<1)
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#define FORCE_LNK_PN (1<<0)
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#define IPG_CFG_NORMAL (0)
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#define IPG_CFG_SHORT (1)
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#define IPG_CFG_64BITS (0x2)
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#define PN_SPEED_10M (0)
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#define PN_SPEED_100M (1)
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#define PN_SPEED_1000M (2)
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/* GSW_PMSR */
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#define EEE1G_STS (1<<7)
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#define EEE100_STS (1<<6)
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#define RX_FC_STS (1<<5)
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#define TX_FC_STS (1<<4)
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#define MAC_SPD_STS_SHIFT (2)
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#define MAC_SPD_STS (0x3<<MAC_SPD_STS_SHIFT)
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#define MAC_DPX_STS (1<<1)
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#define MAC_LINK_STS (1<<0)
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/* GSW_CFG_PPSC */
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#define PHY_AP_EN_SHIFT (1<<24)
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#define PHY_AP_EN (0x7f<<PHY_END_ADDR_SHIFT)
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#define PHY_EEE_EN_SHIFT (1<<16)
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#define PHY_EEE_EN (0x7f<<PHY_END_ADDR_SHIFT)
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#define PHY_PRE_EN (1<<15)
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#define PHY_END_ADDR_SHIFT (8)
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#define PHY_END_ADDR (0x1f<<PHY_END_ADDR_SHIFT)
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#define PHY_MDC_CFG_SHIFT (1<<6)
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#define PHY_MDC_CFG (0x3<<PHY_MDC_CFG_SHIFT)
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#define PHY_ST_ADDR_SHIFT (0)
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#define PHY_ST_ADDR (0x1f<<PHY_ST_ADDR_SHIFT)
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/* GSW_CFG_PIAC */
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#define PHY_ACS_ST (1<<31)
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#define MDIO_REG_ADDR_SHIFT (25)
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#define MDIO_REG_ADDR (0x1f<<MDIO_REG_ADDR_SHIFT)
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#define MDIO_PHY_ADDR_SHIFT (20)
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#define MDIO_PHY_ADDR (0x1f<<MDIO_PHY_ADDR_SHIFT)
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#define MDIO_CMD_SHIFT (18)
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#define MDIO_CMD (0x3<<MDIO_CMD_SHIFT)
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#define MDIO_ST_SHIFT (16)
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#define MDIO_ST (0x3<<MDIO_ST_SHIFT)
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#define MDIO_RW_DATA_SHIFT (0)
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#define MDIO_RW_DATA (0xffff<<MDIO_RW_DATA_SHIFT)
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#define PHY_ACS_ST_START (1)
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#define MDIO_CMD_WRITE (1)
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#define MDIO_CMD_READ (2)
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#define MDIO_ST_START (1)
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#define MDIO_CL45_CMD_ADDR (0)
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#define MDIO_CL45_CMD_WRITE (1)
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#define MDIO_CL45_CMD_READ (3)
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#define MDIO_CL45_CMD_POSTREAD_INCADDR (2)
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#define MDIO_CL45_ST_START (0)
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#define NORMAL_READ (1<<0)
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#define POST_READ (1<<1)
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/* GSW_CFG_GPC */
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#define RX_CLK_MODE (1<<2)
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#define IRQ_CFG_RINGIDX_SHIFT (16)
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#define IRQ_CFG_RINGIDX_MASK (0x1<<IRQ_CFG_RINGIDX_SHIFT)
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#define IRQ_CFG_IDX_MASK 0xFFF
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/* QDMA_CSR_IRQ_STATUS(base) */
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#define IRQ_STATUS_ENTRY_LEN_SHIFT (16)
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#define IRQ_STATUS_ENTRY_LEN_MASK (0xFFF<<IRQ_STATUS_ENTRY_LEN_SHIFT)
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#define IRQ_STATUS_HEAD_IDX_SHIFT (0)
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#define IRQ_STATUS_HEAD_IDX_MASK (0xFFF<<IRQ_STATUS_HEAD_IDX_SHIFT)
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/* QDMA_CSR_INT_ENABLE(base) */
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#define INT_MASK_XPON_PHY (1<<24)
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#define INT_MASK_EPON_MAC (1<<17)
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#define INT_MASK_GPON_MAC (1<<16)
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#define INT_MASK_RX1_COHERENT (1<<15)
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#define INT_MASK_TX1_COHERENT (1<<14)
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#define INT_MASK_RX0_COHERENT (1<<13)
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#define INT_MASK_TX0_COHERENT (1<<12)
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#define INT_MASK_IRQ_FULL (1<<9)
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#define INT_MASK_HWFWD_DSCP_LOW (1<<8)
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#define INT_MASK_NO_RX1_CPU_DSCP (1<<7)
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#define INT_MASK_NO_TX1_CPU_DSCP (1<<6)
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#define INT_MASK_RX1_DONE (1<<5)
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#define INT_MASK_TX1_DONE (1<<4)
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#define INT_MASK_NO_RX0_CPU_DSCP (1<<3)
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#define INT_MASK_NO_TX0_CPU_DSCP (1<<2)
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#define INT_MASK_RX0_DONE (1<<1)
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#define INT_MASK_TX0_DONE (1<<0)
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/* RSTCTRL2 */
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#define QDMA1_RST (1<<1)
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#define QDMA2_RST (1<<2)
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#define FE_RST (1<<21)
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#define ESW_RST (1<<23)
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/* SCU */
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#define IOMUX_CONTROL1 0xBFA20104
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#define RG_7530_RSTN 0xBFA200F8
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#define MT7530_RST (1)
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