223 lines
7.1 KiB
C
Executable File
223 lines
7.1 KiB
C
Executable File
/* $Id: //BBN_Linux/Branch/Branch_for_Rel_TP_ASEAN_20161216/tclinux_phoenix/bootrom/bootram/include/asm/ng1hw.h#1 $
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*
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* ng1hw.h: Tweaks the newport.h structures and definations to be compatible
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* with IRIX. Quite ugly, but it works.
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*
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* Copyright (C) 1999 Ulf Carlsson (ulfc@thepuffingroup.com)
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*
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*/
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#ifndef _SGI_NG1HW_H
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#define _SGI_NG1HW_H
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#include <video/newport.h>
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#define rex3regs newport_rexregs
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#define configregs newport_cregs
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#define float_long npfreg_t
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typedef struct newport_rexregs Rex3regs;
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typedef struct newport_cregs Configregs;
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typedef union np_dcb DCB_reg;
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/* It looks like I can't do a simple tweak with this structure because the IRIX
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* version is just *too* stupid. Ok, here's a new version of it..
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*/
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struct rex3chip {
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struct newport_rexregs set;
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unsigned long _unused0[0x16e];
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struct newport_rexregs go;
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unsigned long _unused1[0x22e];
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struct {
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struct newport_cregs set;
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unsigned long _unused2[0x1ef];
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struct newport_cregs go;
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} p1;
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};
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typedef struct rex3chip rex3Chip;
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typedef struct rex3chip Rex3chip;
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/* Tweak the defines .. */
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#define DM0_OPCODE NPORT_DMODE0_OPMASK
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#define DM0_NOP NPORT_DMODE0_NOP
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#define DM0_READ NPORT_DMODE0_RD
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#define DM0_DRAW NPORT_DMODE0_DRAW
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#define DM0_SCR2SCR NPORT_DMODE0_S2S
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#define DM0_ADRMODE_SHIFT 2
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#define DM0_ADRMODE NPORT_DMODE0_AMMASK
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#define DM0_SPAN NPORT_DMODE0_SPAN
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#define DM0_BLOCK NPORT_DMODE0_BLOCK
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#define DM0_ILINE NPORT_DMODE0_ILINE
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#define DM0_FLINE NPORT_DMODE0_FLINE
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#define DM0_ALINE NPORT_DMODE0_ALINE
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#define DM0_TLINE NPORT_DMODE0_TLINE
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#define DM0_BLINE NPORT_DMODE0_BLINE
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#define DM0_DOSETUP NPORT_DMODE0_DOSETUP
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#define DM0_COLORHOST NPORT_DMODE0_CHOST
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#define DM0_ALPHAHOST NPORT_DMODE0_AHOST
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#define DM0_STOPONX NPORT_DMODE0_STOPX
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#define DM0_STOPONY NPORT_DMODE0_STOPY
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#define DM0_STOPONXY (NPORT_DMODE0_STOPX | NPORT_DMODE0_STOPY)
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#define DM0_SKIPFIRST NPORT_DMODE0_SK1ST
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#define DM0_SKIPLAST NPORT_DMODE0_SKLST
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#define DM0_ENZPATTERN NPORT_DMODE0_ZPENAB
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#define DM0_ENLSPATTERN NPORT_DMODE0_LISPENAB
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#define DM0_LSADVLAST NPORT_DMODE0_LISLST
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#define DM0_LENGTH32 NPORT_DMODE0_L32
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#define DM0_ZOPAQUE NPORT_DMODE0_ZOPQ
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#define DM0_LSOPAQUE NPORT_DMODE0_LISOPQ
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#define DM0_SHADE NPORT_DMODE0_SHADE
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#define DM0_LRONLY NPORT_DMODE0_LRONLY
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#define DM0_XYOFFSET NPORT_DMODE0_XYOFF
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#define DM0_CICLAMP NPORT_DMODE0_CLAMP
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#define DM0_ENDPTFILTER NPORT_DMODE0_ENDPF
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#define DM0_YSTRIDE NPORT_DMODE0_YSTR
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#define DM1_PLANES_SHIFT 0
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/* The rest of the DM1 planes defines are in newport.h */
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#define DM1_DRAWDEPTH_SHIFT 3
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#define DM1_DRAWDEPTH_MASK NPORT_DMODE1_DDMASK
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#define DM1_DRAWDEPTH NPORT_DMODE1_DD24 /* An alias? */
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#define DM1_DRAWDEPTH4 NPORT_DMODE1_DD4
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#define DM1_DRAWDEPTH8 NPORT_DMODE1_DD8
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#define DM1_DRAWDEPTH12 NPORT_DMODE1_DD12
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#define DM1_DRAWDEPTH24 NPORT_DMODE1_DD24
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#define DM1_DBLSRC NPORT_DMODE1_DSRC
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#define DM1_YFLIP NPORT_DMODE1_YFLIP
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#define DM1_RWPACKED NPORT_DMODE1_RWPCKD
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#define DM1_HOSTDEPTH_SHIFT 8
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#define DM1_HOSTDEPTH_MASK NPORT_DMODE1_HDMASK
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#define DM1_HOSTDEPTH NPORT_DMODE1_HD32 /* An alias? */
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#define DM1_HOSTDEPTH4 NPORT_DMODE1_HD4
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#define DM1_HOSTDEPTH8 NPORT_DMODE1_HD8
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#define DM1_HOSTDEPTH12 NPORT_DMODE1_HD12
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#define DM1_HOSTDEPTH32 NPORT_DMODE1_HD32
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#define DM1_RWDOUBLE NPORT_DMODE1_RWDBL
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#define DM1_SWAPENDIAN NPORT_DMODE1_ESWAP
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#define DM1_COLORCOMPARE_SHIFT 12
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#define DM1_COLORCOMPARE_MASK NPORT_DMODE1_CCMASK
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#define DM1_COLORCOMPARE NPORT_DMODE1_CCMASK
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#define DM1_COLORCOMPLT NPORT_DMODE1_CCLT
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#define DM1_COLORCOMPEQ NPORT_DMODE1_CCEQ
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#define DM1_COLORCOMPGT NPORT_DMODE1_CCGT
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#define DM1_RGBMODE NPORT_DMODE1_RGBMD
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#define DM1_ENDITHER NPORT_DMODE1_DENAB
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#define DM1_FASTCLEAR NPORT_DMODE1_FCLR
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#define DM1_ENBLEND NPORT_DMODE1_BENAB
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#define DM1_SF_SHIFT 19
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#define DM1_SF_MASK NPORT_DMODE1_SFMASK
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#define DM1_SF NPORT_DMODE1_SFMASK
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#define DM1_SF_ZERO NPORT_DMODE1_SF0
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#define DM1_SF_ONE NPORT_DMODE1_SF1
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#define DM1_SF_DC NPORT_DMODE1_SFDC
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#define DM1_SF_MDC NPORT_DMODE1_SFMDC
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#define DM1_SF_SA NPORT_DMODE1_SFSA
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#define DM1_SF_MSA NPORT_DMODE1_SFMSA
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#define DM1_DF_SHIFT 22 /* dfactor(2:0) */
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#define DM1_DF_MASK NPORT_DMODE1_DFMASK
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#define DM1_DF NPORT_DMODE1_DFMASK
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#define DM1_DF_ZERO NPORT_DMODE1_DF0
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#define DM1_DF_ONE NPORT_DMODE1_DF1
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#define DM1_DF_SC NPORT_DMODE1_DFSC
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#define DM1_DF_MSC NPORT_DMODE1_DFMSC
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#define DM1_DF_SA NPORT_DMODE1_DFSA
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#define DM1_DF_MSA NPORT_DMODE1_DFMSA
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#define DM1_ENBACKBLEND NPORT_DMODE1_BBENAB
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#define DM1_ENPREFETCH NPORT_DMODE1_PFENAB
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#define DM1_BLENDALPHA NPORT_DMODE1_ABLEND
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#define DM1_LO_SHIFT 28
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#define DM1_LO NPORT_DMODE1_LOMASK
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#define DM1_LO_MASK NPORT_DMODE1_LOMASK
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#define DM1_LO_ZERO NPORT_DMODE1_LOZERO
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#define DM1_LO_AND NPORT_DMODE1_LOAND
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#define DM1_LO_ANDR NPORT_DMODE1_LOANDR
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#define DM1_LO_SRC NPORT_DMODE1_LOSRC
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#define DM1_LO_ANDI NPORT_DMODE1_LOANDI
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#define DM1_LO_DST NPORT_DMODE1_LODST
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#define DM1_LO_XOR NPORT_DMODE1_LOXOR
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#define DM1_LO_OR NPORT_DMODE1_LOOR
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#define DM1_LO_NOR NPORT_DMODE1_LONOR
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#define DM1_LO_XNOR NPORT_DMODE1_LOXNOR
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#define DM1_LO_NDST NPORT_DMODE1_LONDST
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#define DM1_LO_ORR NPORT_DMODE1_LOORR
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#define DM1_LO_NSRC NPORT_DMODE1_LONSRC
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#define DM1_LO_ORI NPORT_DMODE1_LOORI
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#define DM1_LO_NAND NPORT_DMODE1_LONAND
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#define DM1_LO_ONE NPORT_DMODE1_LOONE
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#define SMASK0 NPORT_CMODE_SM0
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#define SMASK1 NPORT_CMODE_SM1
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#define SMASK2 NPORT_CMODE_SM2
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#define SMASK3 NPORT_CMODE_SM3
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#define SMASK4 NPORT_CMODE_SM4
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#define ALL_SMASKS 0x1f
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#define CM_CIDMATCH_SHIFT 9
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#define CM_CIDMATCH_MASK NPORT_CMODE_CMSK
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#define REX3VERSION_MASK NPORT_STAT_VERS
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#define GFXBUSY NPORT_STAT_GBUSY
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#define BACKBUSY NPORT_STAT_BBUSY
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#define VRINT NPORT_STAT_VRINT
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#define VIDEOINT NPORT_STAT_VIDINT
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#define GFIFO_LEVEL_SHIFT 7
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#define GFIFO_LEVEL_MASK NPORT_STAT_GLMSK
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#define BFIFO_LEVEL_SHIFT 13
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#define BFIFO_LEVEL_MASK NPORT_STAT_BLMSK
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#define BFIFO_INT NPORT_STAT_BFIRQ
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#define GFIFO_INT NPORT_STAT_GFIRQ
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#define GIO32MODE NPORT_CFG_G32MD
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#define BUSWIDTH NPORT_CFG_BWIDTH
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#define EXTREGXCVR NPORT_CFG_ERCVR
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#define BFIFODEPTH_SHIFT 3
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#define BFIFODEPTH_MASK NPORT_CFG_BDMSK
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#define BFIFOABOVEINT NPORT_CFG_BFAINT
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#define GFIFODEPTH_SHIFT 8
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#define GFIFODEPTH_MASK NPORT_CFG_GDMSK
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#define GFIFOABOVEINT NPORT_CFG_GFAINT
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#define TIMEOUT_SHIFT 14
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#define TIMEOUT_MASK NPORT_CFG_TOMSK
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#define VREFRESH_SHIFT 17
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#define VREFRESH_MASK NPORT_CFG_VRMSK
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#define FB_TYPE NPORT_CFG_FBTYP
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#define DCB_DATAWIDTH_MASK (0x3)
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#define DCB_CRS_MASK (0x7 << DCB_CRS_SHIFT)
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#define DCB_ADDR_MASK (0xf << DCB_ADDR_SHIFT)
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#define DCB_CSWIDTH_MASK (0x1f << DCB_CSWIDTH_SHIFT)
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#define DCB_CSHOLD_MASK (0x1f << DCB_CSHOLD_SHIFT)
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#define DCB_CSSETUP_MASK (0x1f << DCB_CSSETUP_SHIFT)
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#define DCB_SWAPENDIAN (1 << 28)
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#define REX3WAIT(rex3) while ((rex3)->p1.set.status & GFXBUSY)
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#define BFIFOWAIT(rex3) while ((rex3)->p1.set.status & BACKBUSY)
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#define REX3_GIO_ADDR_0 0x1f0f0000
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#define REX3_GIO_ADDR_1 0x1f4f0000
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#define REX3_GIO_ADDR_2 0x1f8f0000
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#define REX3_GIO_ADDR_3 0x1fcf0000
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#define NG1_XSIZE 1280
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#define NG1_YSIZE 1024
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#endif
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