136 lines
4.2 KiB
C
Executable File
136 lines
4.2 KiB
C
Executable File
/*
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* cpu.h: Values of the PRId register used to match up
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* various MIPS cpu types.
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*
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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*/
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#ifndef _ASM_CPU_H
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#define _ASM_CPU_H
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#include <asm/cache.h>
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/* Assigned Company values for bits 23:16 of the PRId Register
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(CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
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MTI, the PRId register is defined in this (backwards compatible)
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way:
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+----------------+----------------+----------------+----------------+
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| Company Options| Company ID | Processor ID | Revision |
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+----------------+----------------+----------------+----------------+
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31 24 23 16 15 8 7
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I don't have docs for all the previous processors, but my impression is
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that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
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spec.
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*/
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#define PRID_COMP_LEGACY 0x000000
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#define PRID_COMP_MIPS 0x010000
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#define PRID_COMP_ALCHEMY 0x030000
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/*
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* Don't know who should be here...QED and Sandcraft, maybe?
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*/
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#define PRID_COMP_SIBYTE 0x040000
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/*
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* Assigned values for the product ID register. In order to detect a
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* certain CPU type exactly eventually additional registers may need to
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* be examined. These are valid when 23:16 == PRID_COMP_LEGACY
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*/
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#define PRID_IMP_R2000 0x0100
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#define PRID_IMP_AU1000 0x0100
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#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
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#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
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#define PRID_IMP_R4000 0x0400
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#define PRID_IMP_R6000A 0x0600
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#define PRID_IMP_R10000 0x0900
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#define PRID_IMP_R4300 0x0b00
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#define PRID_IMP_VR41XX 0x0c00
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#define PRID_IMP_R12000 0x0e00
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#define PRID_IMP_R8000 0x1000
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#define PRID_IMP_R4600 0x2000
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#define PRID_IMP_R4700 0x2100
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#define PRID_IMP_TX39 0x2200
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#define PRID_IMP_R4640 0x2200
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#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
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#define PRID_IMP_R5000 0x2300
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#define PRID_IMP_SONIC 0x2400
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#define PRID_IMP_MAGIC 0x2500
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#define PRID_IMP_RM7000 0x2700
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#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
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#define PRID_IMP_R5432 0x5400
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#define PRID_IMP_4KC 0x8000
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#define PRID_IMP_5KC 0x8100
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#define PRID_IMP_4KEC 0x8400
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#define PRID_IMP_4KSC 0x8600
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#define PRID_IMP_UNKNOWN 0xff00
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/*
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* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
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*/
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#define PRID_IMP_SB1 0x0100
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/*
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* Definitions for 7:0 on legacy processors
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*/
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#define PRID_REV_R4400 0x0040
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#define PRID_REV_R3000A 0x0030
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#define PRID_REV_R3000 0x0020
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#define PRID_REV_R2000A 0x0010
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#define PRID_REV_TX3912 0x0010
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#define PRID_REV_TX3922 0x0030
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#define PRID_REV_TX3927 0x0040
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#ifndef _LANGUAGE_ASSEMBLY
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/*
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* Capability and feature descriptor structure for MIPS CPU
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*/
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struct mips_cpu {
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unsigned int processor_id;
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unsigned int cputype; /* Old "mips_cputype" code */
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int isa_level;
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int options;
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/* int tlbsize; */ /* lobo del */
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struct cache_desc icache; /* Primary I-cache */
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struct cache_desc dcache; /* Primary D or combined I/D cache */
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struct cache_desc scache; /* Secondary cache */
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struct cache_desc tcache; /* Tertiary/split secondary cache */
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};
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#endif
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/*
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* ISA Level encodings
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*/
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#define MIPS_CPU_ISA_I 0x00000001
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#define MIPS_CPU_ISA_II 0x00000002
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#define MIPS_CPU_ISA_III 0x00000003
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#define MIPS_CPU_ISA_IV 0x00000004
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#define MIPS_CPU_ISA_V 0x00000005
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#define MIPS_CPU_ISA_M32 0x00000020
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#define MIPS_CPU_ISA_M64 0x00000040
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/*
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* CPU Option encodings
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*/
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#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
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#define MIPS_CPU_NOTLB 0x00000000 /* CPU hasn't TLB */ /*lobo add */
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/* Leave a spare bit for variant MMU types... */
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#define MIPS_CPU_4KEX 0x00000004 /* "R4K" exception model */
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#define MIPS_CPU_4KTLB 0x00000008 /* "R4K" TLB handler */
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#define MIPS_CPU_FPU 0x00000010 /* CPU has FPU */
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#define MIPS_CPU_32FPR 0x00000020 /* 32 dbl. prec. FP registers */
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#define MIPS_CPU_COUNTER 0x00000040 /* Cycle count/compare */
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#define MIPS_CPU_WATCH 0x00000080 /* watchpoint registers */
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#define MIPS_CPU_MIPS16 0x00000100 /* code compression */
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#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
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#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
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#define MIPS_CPU_CACHE_CDEX 0x00000800 /* Create_Dirty_Exclusive CACHE op */
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#endif /* _ASM_CPU_H */
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