636 lines
24 KiB
C
Executable File
636 lines
24 KiB
C
Executable File
/*
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*
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* BRIEF MODULE DESCRIPTION
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* Include file for Alchemy Semiconductor's Au1000 CPU.
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*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _AU1000_H_
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#define _AU1000_H_
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/* SDRAM Controller */
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#define CS_MODE_0 0x14000000
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#define CS_MODE_1 0x14000004
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#define CS_MODE_2 0x14000008
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#define CS_CONFIG_0 0x1400000C
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#define CS_CONFIG_1 0x14000010
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#define CS_CONFIG_2 0x14000014
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#define REFRESH_CONFIG 0x14000018
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#define PRECHARGE_CMD 0x1400001C
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#define AUTO_REFRESH_CMD 0x14000020
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#define WRITE_EXTERN_0 0x14000024
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#define WRITE_EXTERN_1 0x14000028
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#define WRITE_EXTERN_2 0x1400002C
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#define SDRAM_SLEEP 0x14000030
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#define TOGGLE_CKE 0x14000034
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/* Static Bus Controller */
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#define STATIC_CONFIG_0 0x14001000
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#define STATIC_TIMING_0 0x14001004
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#define STATIC_ADDRESS_0 0x14001008
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#define STATIC_CONFIG_1 0x14001010
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#define STATIC_TIMING_1 0x14001014
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#define STATIC_ADDRESS_1 0x14001018
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#define STATIC_CONFIG_2 0x14001020
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#define STATIC_TIMING_2 0x14001024
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#define STATIC_ADDRESS_2 0x14001028
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#define STATIC_CONFIG_3 0x14001030
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#define STATIC_TIMING_3 0x14001034
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#define STATIC_ADDRESS_3 0x14001038
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/* DMA Controller 0 */
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#define DMA0_MODE_SET 0x14002000
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#define DMA0_MODE_CLEAR 0x14002004
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#define DMA0_PERIPHERAL_ADDR 0x14002008
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#define DMA0_BUFFER0_START 0x1400200C
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#define DMA0_BUFFER0_COUNT 0x14002010
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#define DMA0_BUFFER1_START 0x14002014
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#define DMA0_BUFFER1_COUNT 0x14002018
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/* DMA Controller 1 */
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#define DMA1_MODE_SET 0x14002100
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#define DMA1_MODE_CLEAR 0x14002104
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#define DMA1_PERIPHERAL_ADDR 0x14002108
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#define DMA1_BUFFER0_START 0x1400210C
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#define DMA1_BUFFER0_COUNT 0x14002110
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#define DMA1_BUFFER1_START 0x14002114
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#define DMA1_BUFFER1_COUNT 0x14002118
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/* DMA Controller 2 */
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#define DMA2_MODE_SET 0x14002200
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#define DMA2_MODE_CLEAR 0x14002204
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#define DMA2_PERIPHERAL_ADDR 0x14002208
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#define DMA2_BUFFER0_START 0x1400220C
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#define DMA2_BUFFER0_COUNT 0x14002210
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#define DMA2_BUFFER1_START 0x14002214
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#define DMA2_BUFFER1_COUNT 0x14002218
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/* DMA Controller 3 */
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#define DMA3_MODE_SET 0x14002300
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#define DMA3_MODE_CLEAR 0x14002304
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#define DMA3_PERIPHERAL_ADDR 0x14002308
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#define DMA3_BUFFER0_START 0x1400230C
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#define DMA3_BUFFER0_COUNT 0x14002310
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#define DMA3_BUFFER1_START 0x14002314
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#define DMA3_BUFFER1_COUNT 0x14002318
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/* DMA Controller 4 */
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#define DMA4_MODE_SET 0x14002400
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#define DMA4_MODE_CLEAR 0x14002404
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#define DMA4_PERIPHERAL_ADDR 0x14002408
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#define DMA4_BUFFER0_START 0x1400240C
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#define DMA4_BUFFER0_COUNT 0x14002410
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#define DMA4_BUFFER1_START 0x14002414
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#define DMA4_BUFFER1_COUNT 0x14002418
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/* DMA Controller 5 */
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#define DMA5_MODE_SET 0x14002500
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#define DMA5_MODE_CLEAR 0x14002504
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#define DMA5_PERIPHERAL_ADDR 0x14002508
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#define DMA5_BUFFER0_START 0x1400250C
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#define DMA5_BUFFER0_COUNT 0x14002510
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#define DMA5_BUFFER1_START 0x14002514
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#define DMA5_BUFFER1_COUNT 0x14002518
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/* DMA Controller 6 */
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#define DMA6_MODE_SET 0x14002600
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#define DMA6_MODE_CLEAR 0x14002604
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#define DMA6_PERIPHERAL_ADDR 0x14002608
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#define DMA6_BUFFER0_START 0x1400260C
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#define DMA6_BUFFER0_COUNT 0x14002610
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#define DMA6_BUFFER1_START 0x14002614
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#define DMA6_BUFFER1_COUNT 0x14002618
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/* DMA Controller 7 */
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#define DMA7_MODE_SET 0x14002700
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#define DMA7_MODE_CLEAR 0x14002704
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#define DMA7_PERIPHERAL_ADDR 0x14002708
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#define DMA7_BUFFER0_START 0x1400270C
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#define DMA7_BUFFER0_COUNT 0x14002710
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#define DMA7_BUFFER1_START 0x14002714
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#define DMA7_BUFFER1_COUNT 0x14002718
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/* Interrupt Controller 0 */
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#define INTC0_CONFIG0_READ 0x10400040
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#define INTC0_CONFIG0_SET 0x10400040
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#define INTC0_CONFIG0_CLEAR 0x10400044
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#define INTC0_CONFIG1_READ 0x10400048
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#define INTC0_CONFIG1_SET 0x10400048
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#define INTC0_CONFIG1_CLEAR 0x1040004C
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#define INTC0_CONFIG2_READ 0x10400050
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#define INTC0_CONFIG2_SET 0x10400050
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#define INTC0_CONFIG2_CLEAR 0x10400054
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#define INTC0_REQ0_INT 0x10400054
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#define INTC0_SOURCE_READ 0x10400058
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#define INTC0_SOURCE_SET 0x10400058
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#define INTC0_SOURCE_CLEAR 0x1040005C
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#define INTC0_REQ1_INT 0x1040005C
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#define INTC0_ASSIGN_REQ_READ 0x10400060
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#define INTC0_ASSIGN_REQ_SET 0x10400060
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#define INTC0_ASSIGN_REQ_CLEAR 0x10400064
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#define INTC0_WAKEUP_READ 0x10400068
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#define INTC0_WAKEUP_SET 0x10400068
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#define INTC0_WAKEUP_CLEAR 0x1040006C
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#define INTC0_MASK_READ 0x10400070
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#define INTC0_MASK_SET 0x10400070
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#define INTC0_MASK_CLEAR 0x10400074
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#define INTC0_R_EDGE_DETECT 0x10400078
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#define INTC0_R_EDGE_DETECT_CLEAR 0x10400078
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#define INTC0_F_EDGE_DETECT_CLEAR 0x1040007C
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#define INTC0_TEST_BIT 0x10400080
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/* Interrupt Controller 1 */
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#define INTC1_CONFIG0_READ 0x11800040
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#define INTC1_CONFIG0_SET 0x11800040
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#define INTC1_CONFIG0_CLEAR 0x11800044
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#define INTC1_CONFIG1_READ 0x11800048
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#define INTC1_CONFIG1_SET 0x11800048
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#define INTC1_CONFIG1_CLEAR 0x1180004C
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#define INTC1_CONFIG2_READ 0x11800050
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#define INTC1_CONFIG2_SET 0x11800050
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#define INTC1_CONFIG2_CLEAR 0x11800054
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#define INTC1_REQ0_INT 0x11800054
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#define INTC1_SOURCE_READ 0x11800058
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#define INTC1_SOURCE_SET 0x11800058
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#define INTC1_SOURCE_CLEAR 0x1180005C
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#define INTC1_REQ1_INT 0x1180005C
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#define INTC1_ASSIGN_REQ_READ 0x11800060
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#define INTC1_ASSIGN_REQ_SET 0x11800060
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#define INTC1_ASSIGN_REQ_CLEAR 0x11800064
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#define INTC1_WAKEUP_READ 0x11800068
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#define INTC1_WAKEUP_SET 0x11800068
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#define INTC1_WAKEUP_CLEAR 0x1180006C
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#define INTC1_MASK_READ 0x11800070
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#define INTC1_MASK_SET 0x11800070
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#define INTC1_MASK_CLEAR 0x11800074
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#define INTC1_R_EDGE_DETECT 0x11800078
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#define INTC1_R_EDGE_DETECT_CLEAR 0x11800078
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#define INTC1_F_EDGE_DETECT_CLEAR 0x1180007C
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#define INTC1_TEST_BIT 0x11800080
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/* Interrupt Configuration Modes */
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#define INTC_INT_DISABLED 0
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#define INTC_INT_RISE_EDGE 0x1
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#define INTC_INT_FALL_EDGE 0x2
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#define INTC_INT_RISE_AND_FALL_EDGE 0x3
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#define INTC_INT_HIGH_LEVEL 0x5
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#define INTC_INT_LOW_LEVEL 0x6
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#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
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/* Interrupt Numbers */
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#define AU1000_UART0_INT 0
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#define AU1000_UART1_INT 1
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#define AU1000_UART2_INT 2
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#define AU1000_UART3_INT 3
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#define AU1000_SSI0_INT 4
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#define AU1000_SSI1_INT 5
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#define AU1000_DMA0_INT 6
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#define AU1000_DMA1_INT 7
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#define AU1000_DMA2_INT 8
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#define AU1000_DMA3_INT 9
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#define AU1000_DMA4_INT 10
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#define AU1000_DMA5_INT 11
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#define AU1000_DMA6_INT 12
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#define AU1000_DMA7_INT 13
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#define AU1000_PC0_INT 14
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#define AU1000_PC0_MATCH0_INT 15
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#define AU1000_PC0_MATCH1_INT 16
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#define AU1000_PC0_MATCH2_INT 17
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#define AU1000_PC1_INT 18
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#define AU1000_PC1_MATCH0_INT 19
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#define AU1000_PC1_MATCH1_INT 20
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#define AU1000_PC1_MATCH2_INT 21
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#define AU1000_IRDA_TX_INT 22
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#define AU1000_IRDA_RX_INT 23
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#define AU1000_USB_DEV_REQ_INT 24
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#define AU1000_USB_DEV_SUS_INT 25
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#define AU1000_USB_HOST_INT 26
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#define AU1000_ACSYNC_INT 27
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#define AU1000_MAC0_DMA_INT 28
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#define AU1000_MAC1_DMA_INT 29
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#define AU1000_ETH0_IRQ AU1000_MAC0_DMA_INT
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#define AU1000_ETH1_IRQ AU1000_MAC1_DMA_INT
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#define AU1000_I2S_UO_INT 30
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#define AU1000_AC97_INT 31
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#define AU1000_LAST_INTC0_INT AU1000_AC97_INT
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#define AU1000_GPIO_0 32
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#define AU1000_GPIO_1 33
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#define AU1000_GPIO_2 34
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#define AU1000_GPIO_3 35
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#define AU1000_GPIO_4 36
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#define AU1000_GPIO_5 37
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#define AU1000_GPIO_6 38
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#define AU1000_GPIO_7 39
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#define AU1000_GPIO_8 40
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#define AU1000_GPIO_9 41
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#define AU1000_GPIO_10 42
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#define AU1000_GPIO_11 43
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#define AU1000_GPIO_12 44
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#define AU1000_GPIO_13 45
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#define AU1000_GPIO_14 46
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#define AU1000_GPIO_15 47
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#define AU1000_GPIO_16 48
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#define AU1000_GPIO_17 49
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#define AU1000_GPIO_18 50
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#define AU1000_GPIO_19 51
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#define AU1000_GPIO_20 52
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#define AU1000_GPIO_21 53
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#define AU1000_GPIO_22 54
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#define AU1000_GPIO_23 55
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#define AU1000_GPIO_24 56
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#define AU1000_GPIO_25 57
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#define AU1000_GPIO_26 58
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#define AU1000_GPIO_27 59
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#define AU1000_GPIO_28 60
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#define AU1000_GPIO_29 61
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#define AU1000_GPIO_30 62
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#define AU1000_GPIO_31 63
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/* Programmable Counters 0 and 1 */
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#define PC_BASE 0x11900000
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#define PC_COUNTER_CNTRL (PC_BASE + 0x14)
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#define PC_CNTRL_E1S (1<<23)
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#define PC_CNTRL_T1S (1<<20)
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#define PC_CNTRL_M21 (1<<19)
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#define PC_CNTRL_M11 (1<<18)
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#define PC_CNTRL_M01 (1<<17)
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#define PC_CNTRL_C1S (1<<16)
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#define PC_CNTRL_BP (1<<14)
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#define PC_CNTRL_EN1 (1<<13)
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#define PC_CNTRL_BT1 (1<<12)
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#define PC_CNTRL_EN0 (1<<11)
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#define PC_CNTRL_BT0 (1<<10)
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#define PC_CNTRL_E0 (1<<8)
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#define PC_CNTRL_E0S (1<<7)
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#define PC_CNTRL_32S (1<<5)
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#define PC_CNTRL_T0S (1<<4)
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#define PC_CNTRL_M20 (1<<3)
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#define PC_CNTRL_M10 (1<<2)
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#define PC_CNTRL_M00 (1<<1)
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#define PC_CNTRL_C0S (1<<0)
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/* Programmable Counter 0 Registers */
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#define PC0_TRIM (PC_BASE + 0)
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#define PC0_COUNTER_WRITE (PC_BASE + 4)
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#define PC0_MATCH0 (PC_BASE + 8)
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#define PC0_MATCH1 (PC_BASE + 0xC)
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#define PC0_MATCH2 (PC_BASE + 0x10)
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#define PC0_COUNTER_READ (PC_BASE + 0x40)
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/* Programmable Counter 1 Registers */
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#define PC1_TRIM (PC_BASE + 0x44)
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#define PC1_COUNTER_WRITE (PC_BASE + 0x48)
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#define PC1_MATCH0 (PC_BASE + 0x4C)
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#define PC1_MATCH1 (PC_BASE + 0x50)
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#define PC1_MATCH2 (PC_BASE + 0x54)
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#define PC1_COUNTER_READ (PC_BASE + 0x58)
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/* I2S Controller */
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#define I2S_DATA 0x11000000
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#define I2S_CONFIG_STATUS 0x11000001
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#define I2S_CONTROL 0x11000002
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/* Ethernet Controllers */
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#define AU1000_ETH0_BASE 0x10500000
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#define AU1000_ETH1_BASE 0x10510000
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/* 4 byte offsets from AU1000_ETH_BASE */
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#define MAC_CONTROL 0x0
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#define MAC_RX_ENABLE (1<<2)
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#define MAC_TX_ENABLE (1<<3)
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#define MAC_DEF_CHECK (1<<5)
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#define MAC_SET_BL(X) (((X)&0x3)<<6)
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#define MAC_AUTO_PAD (1<<8)
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#define MAC_DISABLE_RETRY (1<<10)
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#define MAC_DISABLE_BCAST (1<<11)
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#define MAC_LATE_COL (1<<12)
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#define MAC_HASH_MODE (1<<13)
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#define MAC_HASH_ONLY (1<<15)
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#define MAC_PASS_ALL (1<<16)
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#define MAC_INVERSE_FILTER (1<<17)
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#define MAC_PROMISCUOUS (1<<18)
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#define MAC_PASS_ALL_MULTI (1<<19)
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#define MAC_FULL_DUPLEX (1<<20)
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#define MAC_NORMAL_MODE 0
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#define MAC_INT_LOOPBACK (1<<21)
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#define MAC_EXT_LOOPBACK (1<<22)
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#define MAC_DISABLE_RX_OWN (1<<23)
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#define MAC_BIG_ENDIAN (1<<30)
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#define MAC_RX_ALL (1<<31)
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#define MAC_ADDRESS_HIGH 0x4
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#define MAC_ADDRESS_LOW 0x8
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#define MAC_MCAST_HIGH 0xC
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#define MAC_MCAST_LOW 0x10
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#define MAC_MII_CNTRL 0x14
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#define MAC_MII_BUSY (1<<0)
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#define MAC_MII_READ 0
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#define MAC_MII_WRITE (1<<1)
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#define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
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#define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
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#define MAC_MII_DATA 0x18
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#define MAC_FLOW_CNTRL 0x1C
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#define MAC_FLOW_CNTRL_BUSY (1<<0)
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#define MAC_FLOW_CNTRL_ENABLE (1<<1)
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#define MAC_PASS_CONTROL (1<<2)
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#define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
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#define MAC_VLAN1_TAG 0x20
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#define MAC_VLAN2_TAG 0x24
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/* Ethernet Controller Enable */
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#define MAC0_ENABLE 0x10520000
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#define MAC1_ENABLE 0x10520004
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#define MAC_EN_CLOCK_ENABLE (1<<0)
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#define MAC_EN_RESET0 (1<<1)
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#define MAC_EN_TOSS (1<<2)
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#define MAC_EN_CACHEABLE (1<<3)
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#define MAC_EN_RESET1 (1<<4)
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#define MAC_EN_RESET2 (1<<5)
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#define MAC_DMA_RESET (1<<6)
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/* Ethernet Controller DMA Channels */
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#define MAC0_TX_DMA_ADDR 0x14004000
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#define MAC1_TX_DMA_ADDR 0x14004200
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/* offsets from MAC_TX_RING_ADDR address */
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#define MAC_TX_BUFF0_STATUS 0x0
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#define TX_FRAME_ABORTED (1<<0)
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#define TX_JAB_TIMEOUT (1<<1)
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#define TX_NO_CARRIER (1<<2)
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#define TX_LOSS_CARRIER (1<<3)
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#define TX_EXC_DEF (1<<4)
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#define TX_LATE_COLL_ABORT (1<<5)
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#define TX_EXC_COLL (1<<6)
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#define TX_UNDERRUN (1<<7)
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#define TX_DEFERRED (1<<8)
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#define TX_LATE_COLL (1<<9)
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#define TX_COLL_CNT_MASK (0xF<<10)
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#define TX_PKT_RETRY (1<<31)
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#define MAC_TX_BUFF0_ADDR 0x4
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#define TX_DMA_ENABLE (1<<0)
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#define TX_T_DONE (1<<1)
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#define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
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#define MAC_TX_BUFF0_LEN 0x8
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#define MAC_TX_BUFF1_STATUS 0x10
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#define MAC_TX_BUFF1_ADDR 0x14
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#define MAC_TX_BUFF1_LEN 0x18
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#define MAC_TX_BUFF2_STATUS 0x20
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#define MAC_TX_BUFF2_ADDR 0x24
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#define MAC_TX_BUFF2_LEN 0x28
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#define MAC_TX_BUFF3_STATUS 0x30
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#define MAC_TX_BUFF3_ADDR 0x34
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#define MAC_TX_BUFF3_LEN 0x38
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#define MAC0_RX_DMA_ADDR 0x14004100
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#define MAC1_RX_DMA_ADDR 0x14004300
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/* offsets from MAC_RX_RING_ADDR */
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#define MAC_RX_BUFF0_STATUS 0x0
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#define RX_FRAME_LEN_MASK 0x3fff
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#define RX_WDOG_TIMER (1<<14)
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#define RX_RUNT (1<<15)
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#define RX_OVERLEN (1<<16)
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#define RX_COLL (1<<17)
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#define RX_ETHER (1<<18)
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#define RX_MII_ERROR (1<<19)
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#define RX_DRIBBLING (1<<20)
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#define RX_CRC_ERROR (1<<21)
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#define RX_VLAN1 (1<<22)
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#define RX_VLAN2 (1<<23)
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#define RX_LEN_ERROR (1<<24)
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#define RX_CNTRL_FRAME (1<<25)
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#define RX_U_CNTRL_FRAME (1<<26)
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#define RX_MCAST_FRAME (1<<27)
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#define RX_BCAST_FRAME (1<<28)
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#define RX_FILTER_FAIL (1<<29)
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#define RX_PACKET_FILTER (1<<30)
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#define RX_MISSED_FRAME (1<<31)
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#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
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RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
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RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
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#define MAC_RX_BUFF0_ADDR 0x4
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#define RX_DMA_ENABLE (1<<0)
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#define RX_T_DONE (1<<1)
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#define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
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#define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
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#define MAC_RX_BUFF1_STATUS 0x10
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#define MAC_RX_BUFF1_ADDR 0x14
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#define MAC_RX_BUFF2_STATUS 0x20
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#define MAC_RX_BUFF2_ADDR 0x24
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#define MAC_RX_BUFF3_STATUS 0x30
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#define MAC_RX_BUFF3_ADDR 0x34
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/* UARTS 0-3 */
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#define UART0_ADDR 0x11100000
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#define UART1_ADDR 0x11200000
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#define UART2_ADDR 0x11300000
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#define UART3_ADDR 0x11400000
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#define UART_RX 0 /* Receive buffer */
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#define UART_TX 4 /* Transmit buffer */
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#define UART_IER 8 /* Interrupt Enable Register */
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#define UART_IIR 0xC /* Interrupt ID Register */
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#define UART_FCR 0x10 /* FIFO Control Register */
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#define UART_LCR 0x14 /* Line Control Register */
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#define UART_MCR 0x18 /* Modem Control Register */
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#define UART_LSR 0x1C /* Line Status Register */
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#define UART_MSR 0x20 /* Modem Status Register */
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#define UART_CLK 0x28 /* Baud Rat4e Clock Divider */
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#define UART_MOD_CNTRL 0x100 /* Module Control */
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#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
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#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
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#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
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#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
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#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
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#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
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#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
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#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
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#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
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#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
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#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
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#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
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#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
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/*
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* These are the definitions for the Line Control Register
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*/
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#define UART_LCR_SBC 0x40 /* Set break control */
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#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
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#define UART_LCR_EPAR 0x10 /* Even parity select */
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#define UART_LCR_PARITY 0x08 /* Parity Enable */
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#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
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#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
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#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
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#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
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#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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/*
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* These are the definitions for the Line Status Register
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*/
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */
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#define UART_LSR_FE 0x08 /* Frame error indicator */
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#define UART_LSR_PE 0x04 /* Parity error indicator */
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#define UART_LSR_OE 0x02 /* Overrun error indicator */
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#define UART_LSR_DR 0x01 /* Receiver data ready */
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/*
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* These are the definitions for the Interrupt Identification Register
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*/
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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|
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/*
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* These are the definitions for the Interrupt Enable Register
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*/
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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/*
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* These are the definitions for the Modem Control Register
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*/
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define UART_MCR_OUT2 0x08 /* Out2 complement */
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#define UART_MCR_OUT1 0x04 /* Out1 complement */
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#define UART_MCR_RTS 0x02 /* RTS complement */
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#define UART_MCR_DTR 0x01 /* DTR complement */
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|
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/*
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* These are the definitions for the Modem Status Register
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|
*/
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART_MSR_RI 0x40 /* Ring Indicator */
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#define UART_MSR_DSR 0x20 /* Data Set Ready */
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#define UART_MSR_CTS 0x10 /* Clear to Send */
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#define UART_MSR_DDCD 0x08 /* Delta DCD */
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define UART_MSR_DDSR 0x02 /* Delta DSR */
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#define UART_MSR_DCTS 0x01 /* Delta CTS */
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#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
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|
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/* SSIO */
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#define SSI0_STATUS 0x11600000
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#define SSI0_INT 0x11600004
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#define SSI0_INT_ENABLE 0x11600008
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#define SSI0_CONFIG 0x11600020
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#define SSI0_ADATA 0x11600024
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#define SSI0_CLKDIV 0x11600028
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#define SSI0_CONTROL 0x11600100
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|
|
|
/* SSI1 */
|
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#define SSI1_STATUS 0x11680000
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|
#define SSI1_INT 0x11680004
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|
#define SSI1_INT_ENABLE 0x11680008
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|
#define SSI1_CONFIG 0x11680020
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|
#define SSI1_ADATA 0x11680024
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#define SSI1_CLKDIV 0x11680028
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#define SSI1_CONTROL 0x11680100
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|
|
|
/* IrDA Controller */
|
|
#define IR_RING_PTR_STATUS 0x11500000
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|
#define IR_RING_BASE_ADDR_H 0x11500004
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|
#define IR_RING_BASE_ADDR_L 0x11500008
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|
#define IR_RING_SIZE 0x1150000C
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|
#define IR_RING_PROMPT 0x11500010
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|
#define IR_RING_ADDR_CMPR 0x11500014
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|
#define IR_CONFIG_1 0x11500020
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|
#define IR_SIR_FLAGS 0x11500024
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|
#define IR_ENABLE 0x11500028
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|
#define IR_READ_PHY_CONFIG 0x1150002C
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|
#define IR_WRITE_PHY_CONFIG 0x11500030
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|
#define IR_MAX_PKT_LEN 0x11500034
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|
#define IR_RX_BYTE_CNT 0x11500038
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|
#define IR_CONFIG_2 0x1150003C
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|
#define IR_INTERFACE_CONFIG 0x11500040
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|
|
|
/* GPIO */
|
|
#define TSTATE_STATE_READ 0x11900100
|
|
#define TSTATE_STATE_SET 0x11900100
|
|
#define OUTPUT_STATE_READ 0x11900108
|
|
#define OUTPUT_STATE_SET 0x11900108
|
|
#define OUTPUT_STATE_CLEAR 0x1190010C
|
|
#define PIN_STATE 0x11900110
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|
|
|
/* Power Management */
|
|
#define PM_SCRATCH_0 0x11900018
|
|
#define PM_SCRATCH_1 0x1190001C
|
|
#define PM_WAKEUP_SOURCE_MASK 0x11900034
|
|
#define PM_ENDIANESS 0x11900038
|
|
#define PM_POWERUP_CONTROL 0x1190003C
|
|
#define PM_WAKEUP_CAUSE 0x1190005C
|
|
#define PM_SLEEP_POWER 0x11900078
|
|
#define PM_SLEEP 0x1190007C
|
|
|
|
/* Clock Controller */
|
|
#define FQ_CNTRL_1 0x11900020
|
|
#define FQ_CNTRL_2 0x11900024
|
|
#define CLOCK_SOURCE_CNTRL 0x11900028
|
|
#define CPU_PLL_CNTRL 0x11900060
|
|
#define AUX_PLL_CNTRL 0x11900064
|
|
|
|
/* AC97 Controller */
|
|
#define AC97_CONFIG 0x10000000
|
|
#define AC97_STATUS 0x10000004
|
|
#define AC97_DATA 0x10000008
|
|
#define AC97_CMD 0x1000000C
|
|
#define AC97_CNTRL 0x10000010
|
|
|
|
#endif
|