mirror of
https://github.com/edk2-porting/edk2-msm
synced 2025-06-06 04:01:44 +00:00
73 lines
2.4 KiB
C
Executable File
73 lines
2.4 KiB
C
Executable File
#include <Library/PcdLib.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/HobLib.h>
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#include <Library/SerialPortLib.h>
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#include <Library/PrintLib.h>
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#include <Library/BaseLib.h>
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#include <Library/MemoryMapHelperLib.h>
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#include <Library/PlatformPrePiLib.h>
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#include "PlatformUtils.h"
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VOID InitializeSharedUartBuffers(VOID)
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{
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INTN* pFbConPosition = (INTN*)(FixedPcdGet32(PcdMipiFrameBufferAddress) + (FixedPcdGet32(PcdMipiFrameBufferWidth) *
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FixedPcdGet32(PcdMipiFrameBufferHeight) *
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FixedPcdGet32(PcdMipiFrameBufferPixelBpp) / 8));
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*(pFbConPosition + 0) = 0;
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*(pFbConPosition + 1) = 0;
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}
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VOID UartInit(VOID)
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{
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SerialPortInitialize();
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InitializeSharedUartBuffers();
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DEBUG((EFI_D_INFO, "\nRenegade Project edk2-msm (AArch64)\n"));
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DEBUG(
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(EFI_D_INFO, "Firmware version %s built %a %a\n\n",
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(CHAR16 *)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__));
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}
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VOID ConfigureIOMMUContextBankCacheSetting(
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UINT32 ContextBankId, BOOLEAN CacheCoherent)
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{
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UINT32 ContextBankAddr =
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SMMU_BASE + SMMU_CTX_BANK_0_OFFSET + ContextBankId * SMMU_CTX_BANK_SIZE;
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MmioWrite32(
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ContextBankAddr + SMMU_CTX_BANK_SCTLR_OFFSET,
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CacheCoherent ? SMMU_CCA_SCTLR : SMMU_NON_CCA_SCTLR);
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MmioWrite32(ContextBankAddr + SMMU_CTX_BANK_TTBR0_0_OFFSET, 0);
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MmioWrite32(ContextBankAddr + SMMU_CTX_BANK_TTBR0_1_OFFSET, 0);
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MmioWrite32(ContextBankAddr + SMMU_CTX_BANK_TTBR1_0_OFFSET, 0);
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MmioWrite32(ContextBankAddr + SMMU_CTX_BANK_TTBR1_1_OFFSET, 0);
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MmioWrite32(ContextBankAddr + SMMU_CTX_BANK_MAIR0_OFFSET, 0);
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MmioWrite32(ContextBankAddr + SMMU_CTX_BANK_MAIR1_OFFSET, 0);
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MmioWrite32(ContextBankAddr + SMMU_CTX_BANK_TTBCR_OFFSET, 0);
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}
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VOID SetWatchdogState(BOOLEAN Enable)
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{
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MmioWrite32(APSS_WDT_BASE + APSS_WDT_ENABLE_OFFSET, Enable);
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}
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VOID PlatformInitialize()
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{
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UartInit();
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// Windows requires Cache Coherency for the UFS to work at its best
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// The UFS device is currently attached to the main IOMMU on Context Bank 1
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// (Previous firmware) But said configuration is non cache coherent compliant,
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// fix it.
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ConfigureIOMMUContextBankCacheSetting(UFS_CTX_BANK, TRUE);
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// Disable WatchDog Timer
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SetWatchdogState(FALSE);
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}
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