mirror of
https://github.com/edk2-porting/edk2-msm
synced 2025-05-14 02:42:22 +00:00
404 lines
15 KiB
C
404 lines
15 KiB
C
//===========================================================================
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// <pcie_resources.asl>
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// DESCRIPTION
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// This file contans the resources needed by pcie subsystem.
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//
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//===========================================================================
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Scope(\_SB_.PEP0)
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{
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// PCIe Intra-Soc ports
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Method(PEMD)
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{
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Return (PEMC)
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}
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Name(PEMC,
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package()
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{
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Package()
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{
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"DEVICE",
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"\\_SB.PCI0",
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Package()
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{
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"COMPONENT",
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0x0, // Component 0.
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Package()
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{
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"FSTATE",
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0x0, // f0 state
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},
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Package()
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{
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"FSTATE",
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0x1, // f1 state
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},
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},
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Package()
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{
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"DSTATE",
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0x0, // D0 state
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// PCIE Analog
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package()
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{
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"PMICVREGVOTE", // PMIC VREG resource
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package() // Vote for L28 @1.0v
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{
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"PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
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1, // Voltage Regulator type = LDO
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1200000, // Voltage 1.2V : microvolts ( V )
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1, // Enable = Enable
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1, // Power Mode = NPM
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0, // Head Room
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},
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},
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// PCIE Core
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Package()
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{
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"PMICVREGVOTE",
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Package()
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{
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"PPP_RESOURCE_ID_LDO1_A",
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1, // Voltage Regulator Type, 1 = LDO
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880000, // Voltage (uV)
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1, // Enable = Enable
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1, // Power Mode = NPM
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0, // Headroom
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},
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},
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//Turning on PCIe core
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Package() { "FOOTSWITCH", Package() { "pcie_0_gdsc", 1}},
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// ICB votes through PSTATE
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package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_0_CFG", 75000000, 0}},
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package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_0", "ICBID_SLAVE_EBI1", 400000000, 200000000}},
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package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 1}},
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package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 1}},
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package() {"CLOCK", package() {"gcc_pcie_0_pipe_clk", 1}},
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package() {"CLOCK", package() {"gcc_pcie_0_slv_axi_clk", 1}},
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package() {"CLOCK", package() {"gcc_pcie_0_slv_q2a_axi_clk", 1}},
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package() {"CLOCK", package() {"gcc_pcie_0_mstr_axi_clk", 1}},
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package() {"CLOCK", package() {"gcc_pcie_0_cfg_ahb_clk", 1}},
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package() {"CLOCK", package() {"gcc_pcie_0_aux_clk", 8, 19200000, 3}},
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},
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Package()
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{
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"DSTATE",
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0x1, // D1 state
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},
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Package()
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{
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"DSTATE",
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0x2, // D2 state
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},
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Package()
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{
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"DSTATE",
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0x3, // D3 state
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package() {"CLOCK", package() {"gcc_pcie_0_pipe_clk", 2}},
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package() {"CLOCK", package() {"gcc_pcie_0_aux_clk", 2}},
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package() {"CLOCK", package() {"gcc_pcie_0_slv_axi_clk", 2}},
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package() {"CLOCK", package() {"gcc_pcie_0_slv_q2a_axi_clk", 2}},
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package() {"CLOCK", package() {"gcc_pcie_0_mstr_axi_clk", 2}},
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package() {"CLOCK", package() {"gcc_pcie_0_cfg_ahb_clk", 2}},
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// common clocks
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package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 2}},
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package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 2}},
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// ICB votes
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package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_0_CFG", 0, 0}},
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package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_0", "ICBID_SLAVE_EBI1", 0, 0}},
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// Turn off PCIe core
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Package() { "FOOTSWITCH", Package() { "pcie_0_gdsc", 2}},
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// PCIE Analog
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package()
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{
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"PMICVREGVOTE", // PMIC VREG resource
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package() // Vote for L28 @1.0v
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{
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"PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
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1, // Voltage Regulator type = LDO
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0, // Voltage 1.2V : microvolts ( V )
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0, // Enable = Disable
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0, // Power Mode = NPM
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0, // Head Room
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},
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},
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// PCIE Core
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Package()
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{
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"PMICVREGVOTE",
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Package()
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{
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"PPP_RESOURCE_ID_LDO1_A",
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1, // Voltage Regulator Type, 1 = LDO
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0, // Voltage (uV)
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0, // Enable = Disable
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0, // Power Mode = NPM
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0, // Headroom
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},
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},
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},
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},
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Package()
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{
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"DEVICE",
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"\\_SB.PCI0.RP1",
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Package()
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{
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"COMPONENT",
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0x0, // Component 0
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Package()
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{
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"FSTATE",
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0x0, // f0 state
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},
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Package()
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{
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"FSTATE",
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0x1, // f1 state
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},
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},
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Package()
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{
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"DSTATE",
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0x0, // D0 state
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},
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Package()
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{
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"DSTATE",
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0x1, // D1 state
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},
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Package()
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{
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"DSTATE",
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0x2, // D2 state
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},
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Package()
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{
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"DSTATE",
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0x3, // D3 state
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},
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},
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Package()
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{
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"DEVICE",
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"\\_SB.PCI1",
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Package()
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{
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"COMPONENT",
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0x0, // Component 0.
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Package()
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{
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"FSTATE",
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0x0, // f0 state
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},
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Package()
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{
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"FSTATE",
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0x1, // f1 state
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},
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},
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Package()
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{
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"DSTATE",
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0x0, // D0 state
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// PCIE Analog
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package()
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{
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"PMICVREGVOTE", // PMIC VREG resource
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package() // Vote for L28 @1.0v
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{
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"PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
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1, // Voltage Regulator type = LDO
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1200000, // Voltage 1.2V : microvolts ( V )
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1, // Enable = Enable
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1, // Power Mode = NPM
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0, // Head Room
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},
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},
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// PCIE Core
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Package()
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{
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"PMICVREGVOTE",
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Package()
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{
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"PPP_RESOURCE_ID_LDO1_A",
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1, // Voltage Regulator Type, 1 = LDO
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880000, // Voltage (uV)
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1, // Enable = Enable
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1, // Power Mode = NPM
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0, // Headroom
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},
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},
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//Turning on PCIe core
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Package() { "FOOTSWITCH", Package() { "pcie_1_gdsc", 1}},
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// ICB votes
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package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_1_CFG", 75000000, 0}},
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package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_1", "ICBID_SLAVE_EBI1", 400000000, 200000000}},
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/*
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package()
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{
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"PMICVREGVOTE", // PMICVREGVOTE resource
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package()
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{
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"PPP_RESOURCE_ID_CXO_BUFFERS_LNBBCLK1_A", // Resource ID
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6, // Voltage Regulator type = CXO Buffer
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1, // Force enable from s/w
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0, // Disable pin control
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},
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},
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*/
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package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 1}},
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package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 1}},
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package() {"CLOCK", package() {"gcc_pcie_1_pipe_clk", 1}},
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package() {"CLOCK", package() {"gcc_pcie_1_slv_axi_clk", 1}},
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package() {"CLOCK", package() {"gcc_pcie_1_slv_q2a_axi_clk", 1}},
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package() {"CLOCK", package() {"gcc_pcie_1_mstr_axi_clk", 1}},
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package() {"CLOCK", package() {"gcc_pcie_1_cfg_ahb_clk", 1}},
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package() {"CLOCK", package() {"gcc_pcie_1_aux_clk", 8, 19200000, 3}},
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package() {"CLOCK", package() {"gcc_pcie_phy_refgen_clk", 8, 100000000, 3}},
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},
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Package()
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{
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"DSTATE",
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0x1, // D1 state
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},
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Package()
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{
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"DSTATE",
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0x2, // D2 state
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},
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Package()
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{
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"DSTATE",
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0x3, // D3 state
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package() {"CLOCK", package() {"gcc_pcie_1_pipe_clk", 2}},
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package() {"CLOCK", package() {"gcc_pcie_phy_refgen_clk", 2}},
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package() {"CLOCK", package() {"gcc_pcie_1_aux_clk", 2}},
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package() {"CLOCK", package() {"gcc_pcie_1_slv_axi_clk", 2}},
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package() {"CLOCK", package() {"gcc_pcie_1_slv_q2a_axi_clk", 2}},
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package() {"CLOCK", package() {"gcc_pcie_1_mstr_axi_clk", 2}},
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package() {"CLOCK", package() {"gcc_pcie_1_cfg_ahb_clk", 2}},
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// common clocks
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package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 2}},
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package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 2}},
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// ICB votes
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package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_1_CFG", 0, 0}},
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package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_1", "ICBID_SLAVE_EBI1", 0, 0}},
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// Turn off PCIe core
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Package() { "FOOTSWITCH", Package() { "pcie_1_gdsc", 2}},
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/*
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package()
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{
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"PMICVREGVOTE", // PMICVREGVOTE resource
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package()
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{
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"PPP_RESOURCE_ID_CXO_BUFFERS_LNBBCLK1_A", // Resource ID
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6, // Voltage Regulator type = CXO Buffer
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0, // Force enable from s/w
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0, // Disable pin control
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},
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},
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*/
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// PCIE Analog
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package()
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{
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"PMICVREGVOTE", // PMIC VREG resource
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package() // Vote for L28 @1.0v
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{
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"PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
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1, // Voltage Regulator type = LDO
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0, // Voltage 1.2V : microvolts ( V )
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0, // Enable = Disable
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0, // Power Mode = NPM
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0, // Head Room
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},
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},
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// PCIE Core
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Package()
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{
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"PMICVREGVOTE",
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Package()
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{
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"PPP_RESOURCE_ID_LDO1_A",
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1, // Voltage Regulator Type, 1 = LDO
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0, // Voltage (uV)
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0, // Enable = Disable
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0, // Power Mode = NPM
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0, // Headroom
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},
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},
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},
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},
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Package()
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{
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"DEVICE",
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"\\_SB.PCI1.RP1",
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Package()
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{
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"COMPONENT",
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0x0, // Component 0
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Package()
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{
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"FSTATE",
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0x0, // f0 state
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},
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Package()
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{
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"FSTATE",
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0x1, // f1 state
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},
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},
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Package()
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{
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"DSTATE",
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0x0, // D0 state
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},
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Package()
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{
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"DSTATE",
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0x1, // D1 state
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},
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Package()
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{
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"DSTATE",
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0x2, // D2 state
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},
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Package()
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{
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"DSTATE",
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0x3, // D3 state
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},
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},
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})
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}
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