mirror of
https://github.com/edk2-porting/edk2-msm
synced 2025-05-14 05:02:17 +00:00
444 lines
19 KiB
Plaintext
444 lines
19 KiB
Plaintext
#include "Platform.h"
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#define MAX_OEM_WRITE_ENTRIES 8
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#define DEBUG_DEVICE_PORT_TYPE_SERIAL 0x8000
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#define DEBUG_DEVICE_PORT_TYPE_USB 0x8002
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#define DEBUG_DEVICE_PORT_TYPE_NET 0x8003
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#define DEBUG_DEVICE_PORT_SUBTYPE_SERIAL_QCOM 0x0004
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#define DEBUG_DEVICE_PORT_SUBTYPE_SERIAL_QCOM_S850 0x0011
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#define DEBUG_DEVICE_PORT_SUBTYPE_NET_QCOM 0x5143
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#define DEBUG_DEVICE_PORT_SUBTYPE_USB_QCOM 0x0004
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#define DEBUG_DEVICE_PORT_SUBTYPE_USB30 0x0000
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#define DEBUG_DEVICE_OEM_PORT_USBFN 0x0001
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#define DEBUG_DEVICE_OEM_PORT_USBFN_SYNOPSYS 0x0005
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// Subtype 3 need to be used only if unaligned access to strongly ordered memory isn't supported by hardware.
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// But it works on all hardware so use this value
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#define DEBUG_DEVICE_OEM_PORT_USBFN_BUFFERED 0x0003
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#define NUMBER_OF_DBG_DEVICES 3
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#define MAX_NAME_SPACE_STRING_LENGTH 32
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#define ACPI_DDI_V2_2_REGISTER_CNT 2
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#define ACPI_DDI_V3_REGISTER_CNT 1
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// ACPI structure declarations.
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#pragma pack(1)
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typedef struct {
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UINT8 Revision;
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UINT16 Length;
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UINT8 BaseAddressRegisterCount;
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UINT16 NameSpaceStringLength;
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UINT16 NameSpaceStringOffset;
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UINT16 OemDataLength;
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UINT16 OemDataOffset;
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UINT16 PortType;
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UINT16 PortSubtype;
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UINT16 Reserved;
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UINT16 BaseAddressRegisterOffset;
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UINT16 AddressSizeOffset;
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} ACPI_DEBUG_DEVICE_INFORMATION_V2;
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//
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// v3 Debug Device Information Structure
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//
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typedef struct {
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UINT8 Revision;
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UINT16 Length;
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UINT8 BaseAddressRegisterCount;
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UINT16 NameSpaceStringLength;
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UINT16 NameSpaceStringOffset;
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UINT16 OemDataLength;
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UINT16 OemDataOffset;
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UINT16 PortType;
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UINT16 PortSubtype;
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UINT16 Reserved;
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UINT16 BaseAddressRegisterOffset;
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UINT16 AddressSizeOffset;
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ACPI_GAS DEVICE_ADDRESS;
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UINT32 ADDRESS_SIZE;
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UINT8 NameSpacestring[MAX_NAME_SPACE_STRING_LENGTH];
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} ACPI_DEBUG_DEVICE_INFORMATION_V3;
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typedef struct {
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ACPI_HEADER Header;
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UINT32 OffsetDbgDeviceInfo;
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UINT32 NumberDbgDeviceInfo;
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} ACPI_DEBUG_PORT_TABLE_V2;
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//OEM struct supported by KDNET
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typedef struct {
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UINT16 PortType;
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UINT16 Reserved;
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UINT32 Signature;
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UINT32 WriteCount;
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struct {
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UINT8 BaseAddressRegister;
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UINT8 Width;
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UINT16 Offset;
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UINT32 AndValue;
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UINT32 OrValue;
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} Data[MAX_OEM_WRITE_ENTRIES];
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} ACPI_DEBUG_DEVICE_OEM_DATA;
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//OEM struct for SNPS controller supported by KDNET
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//OEM Phase: 1 = after reset
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// 2 = when configuration is done
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// 3 = on connection done
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typedef struct {
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UINT16 PortType;
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UINT16 Reserved;
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UINT32 Signature;
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UINT32 WriteCount;
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struct {
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UINT8 BaseAddressRegister;
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UINT8 Phase;
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UINT16 Reserved;
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UINT32 Offset;
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UINT32 AndValue;
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UINT32 OrValue;
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} Data[MAX_OEM_WRITE_ENTRIES];
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} ACPI_DEBUG_DEVICE_OEM_DATA_V2;
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// OEM Data Strucutre V3 based upon addition of secondary debugger
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//OEM struct for SNPS controller supported by KDNET
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//OEM Phase: 1 = after reset
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// 2 = when configuration is done
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// 3 = on connection done
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typedef struct {
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UINT16 PortType;
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UINT16 Reserved;
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UINT32 Signature;
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UINT32 WriteCount;
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struct {
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UINT8 BaseAddressRegister;
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UINT8 Phase;
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UINT16 Reserved;
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UINT32 Offset;
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UINT32 AndValue;
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UINT32 OrValue;
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} Data[MAX_OEM_WRITE_ENTRIES];
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struct {
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UINT8 UsbCore;
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UINT8 Reserved1;
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UINT16 Reserved2;
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UINT32 Signature; // = 'USBC'
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} ACPI_USB_INIT_CORE_OEM_DATA;
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} ACPI_DEBUG_DEVICE_OEM_DATA_V3;
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//OEM struct supported by KDUSB, KDNET
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typedef struct {
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UINT32 StructureSize;
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UINT64 GpioPhysicalAddress;
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UINT32 GpioBlockSize;
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UINT32 WriteCount;
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UINT32 Offset[12];
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UINT32 Value[12];
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} OEM_DATA;
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typedef struct {
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ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation;
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// not part of the actual structure
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ACPI_GAS BaseAddressRegister;
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UINT32 AddressSize;
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UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH];
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} ACPI_DEBUG_DEVICE_INFORMATION_V2_IMPL;
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typedef struct {
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ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation;
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// not part of the actual structure
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ACPI_GAS BaseAddressRegister;
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UINT32 AddressSize;
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UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH];
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OEM_DATA OemData;
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} ACPI_DEBUG_DEVICE_INFORMATION_V2_1_OEM_IMPL;
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typedef struct {
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ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation;
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// not part of the actual structure
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ACPI_GAS BaseAddressRegister[ACPI_DDI_V2_2_REGISTER_CNT];
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UINT32 AddressSize[ACPI_DDI_V2_2_REGISTER_CNT];
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UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH];
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ACPI_DEBUG_DEVICE_OEM_DATA OemData;
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} ACPI_DEBUG_DEVICE_INFORMATION_V2_2_OEM_IMPL;
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typedef struct {
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ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation;
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// not part of the actual structure
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ACPI_GAS BaseAddressRegister[ACPI_DDI_V2_2_REGISTER_CNT];
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UINT32 AddressSize[ACPI_DDI_V2_2_REGISTER_CNT];
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UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH];
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ACPI_DEBUG_DEVICE_OEM_DATA_V2 OemData;
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} ACPI_DEBUG_DEVICE_INFORMATION_V2_3_OEM_IMPL;
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typedef struct {
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ACPI_DEBUG_DEVICE_INFORMATION_V2 DebugDeviceInformation;
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// not part of the actual structure
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ACPI_GAS BaseAddressRegister[ACPI_DDI_V2_2_REGISTER_CNT];
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UINT32 AddressSize[ACPI_DDI_V2_2_REGISTER_CNT];
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UINT8 NameSpaceString[MAX_NAME_SPACE_STRING_LENGTH];
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ACPI_DEBUG_DEVICE_OEM_DATA_V3 OemData;
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} ACPI_DEBUG_DEVICE_INFORMATION_V2_4_OEM_IMPL;
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typedef struct {
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ACPI_DEBUG_DEVICE_INFORMATION_V3 DebugDeviceInformation;
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OEM_DATA OemData;
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} ACPI_DEBUG_DEVICE_INFORMATION_V3_OEM_IMPL;
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typedef struct {
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ACPI_DEBUG_PORT_TABLE_V2 DebugPortTable;
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// not part of the actual structure
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ACPI_DEBUG_DEVICE_INFORMATION_V2_IMPL DebugDevice1; // UART KDCOM
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ACPI_DEBUG_DEVICE_INFORMATION_V2_4_OEM_IMPL DebugDevice2; // KDNET on primary port on SNPS controller
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ACPI_DEBUG_DEVICE_INFORMATION_V2_4_OEM_IMPL DebugDevice3; // KDNET on secondary port on SNPS controller
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} ACPI_DEBUG_PORT_TABLE_V2_IMPL;
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#pragma pack()
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// Fixed field values.
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#define ACPI_DDI_V2_REVISION 1
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#define ACPI_DDI_V2_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_IMPL)
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#define ACPI_DDI_V2_1_OEM_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_1_OEM_IMPL)
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#define ACPI_DDI_V2_2_OEM_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_2_OEM_IMPL)
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#define ACPI_DDI_V2_3_OEM_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_3_OEM_IMPL)
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#define ACPI_DDI_V2_4_OEM_LENGTH sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2_4_OEM_IMPL)
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#define ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET sizeof(ACPI_DEBUG_DEVICE_INFORMATION_V2)
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// Structure has only one ACPI_GAS for register (1 base address register)
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#define ACPI_DDI_V2_1_ADDRESS_SIZE_OFFSET ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET + 1 * sizeof(ACPI_GAS)
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#define ACPI_DDI_V2_1_NAMESPACE_STRING_OFFSET ACPI_DDI_V2_1_ADDRESS_SIZE_OFFSET + 1 * sizeof(UINT32)
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#define ACPI_DDI_V2_1_OEM_DATA_OFFSET ACPI_DDI_V2_1_NAMESPACE_STRING_OFFSET + MAX_NAME_SPACE_STRING_LENGTH
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// Structure has ACPI_DDI_V2_2_REGISTER_CNT ACPI_GAS base registers
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// Change this macro ACPI_DDI_V2_2_REGISTER_CNT based upon number of base address register to be used
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#define ACPI_DDI_V2_2_ADDRESS_SIZE_OFFSET ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET + ACPI_DDI_V2_2_REGISTER_CNT * sizeof(ACPI_GAS)
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#define ACPI_DDI_V2_2_NAMESPACE_STRING_OFFSET ACPI_DDI_V2_2_ADDRESS_SIZE_OFFSET + ACPI_DDI_V2_2_REGISTER_CNT * sizeof(UINT32)
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#define ACPI_DDI_V2_2_OEM_DATA_OFFSET ACPI_DDI_V2_2_NAMESPACE_STRING_OFFSET + MAX_NAME_SPACE_STRING_LENGTH
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#define ACPI_DPT_V2_LENGTH sizeof(ACPI_DEBUG_PORT_TABLE_V2_IMPL)
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#define ACPI_DPT_V2_REVISION 1
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// Device namespace strings. (May not be longer than MAX_NAME_SPACE_STRING_LENGTH characters & may not point to same device.)
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#define UART_DEVICE_NAME_SPACE_STRING "\\_SB.UARD"
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#define USB_SS_DEVICE_NAME_SPACE_STRING "\\_SB.URS0" //point to USB3.0 controller
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#define USB_SS1_DEVICE_NAME_SPACE_STRING "\\_SB.USB1" //point to secondary USB3.0 controller
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//URS1 specific
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//#define USB_SS1_DEVICE_NAME_SPACE_STRING "\\_SB.URS1" //point to secondary USB3.0 controller
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// ACPI table definition.
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ACPI_DEBUG_PORT_TABLE_V2_IMPL DBG2 =
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{
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{
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{
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ACPI_DBG2_SIGNATURE, // Signature
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ACPI_DPT_V2_LENGTH, // Length
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ACPI_DPT_V2_REVISION, // Revision
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0, // Checksum
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ACPI_OEM_ID, // OEMID[ACPI_MAX_OEM_ID]
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ACPI_OEM_TABLE_ID, // OEMTableID[ACPI_MAX_TABLE_ID]
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ACPI_OEM_REVISION, // OEMRevision
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ACPI_CREATOR_ID, // CreatorID[ACPI_MAX_CREATOR_ID]
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ACPI_CREATOR_REVISION // CreatorRev
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},
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sizeof(ACPI_DEBUG_PORT_TABLE_V2),
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NUMBER_OF_DBG_DEVICES
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},
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//
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// Debug device table.
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//
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// Device UART
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{
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{
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ACPI_DDI_V2_REVISION, // Revision
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ACPI_DDI_V2_LENGTH, // Length
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1, // BaseAddressRegisterCount
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sizeof(UART_DEVICE_NAME_SPACE_STRING), // NameSpaceStringLength
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ACPI_DDI_V2_1_NAMESPACE_STRING_OFFSET, // NameSpaceStringOffset
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0, // OemDataLength
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0, // OemDataOffset
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DEBUG_DEVICE_PORT_TYPE_SERIAL, // PortType
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DEBUG_DEVICE_PORT_SUBTYPE_SERIAL_QCOM_S850, // PortSubtype
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0, // Reserved
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ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET, // BaseAddressRegisterOffset
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ACPI_DDI_V2_1_ADDRESS_SIZE_OFFSET // AddressSizeOffset
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},
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{
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ACPI_GAS_ID_SYSTEM_MEMORY,
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32,
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0,
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32,
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0xA84000 // BaseAddressRegister
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},
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0x00001000, // AddressSize
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UART_DEVICE_NAME_SPACE_STRING // NameSpaceString
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},
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// Device USB SS as KDNET on primary port (SNPS Controller+ QMP/QUSB2 Phy)
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{
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{
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ACPI_DDI_V2_REVISION, // Revision
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ACPI_DDI_V2_4_OEM_LENGTH, // Length
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ACPI_DDI_V2_2_REGISTER_CNT, // BaseAddressRegisterCount
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sizeof(USB_SS_DEVICE_NAME_SPACE_STRING), // NameSpaceStringLength
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ACPI_DDI_V2_2_NAMESPACE_STRING_OFFSET, // NameSpaceStringOffset
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sizeof(ACPI_DEBUG_DEVICE_OEM_DATA_V3), // OemDataLength
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ACPI_DDI_V2_2_OEM_DATA_OFFSET, // OemDataOffset
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DEBUG_DEVICE_PORT_TYPE_NET, // PortType
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DEBUG_DEVICE_PORT_SUBTYPE_NET_QCOM, // PortSubtype
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0, // Reserved
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ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET, // BaseAddressRegisterOffset
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ACPI_DDI_V2_2_ADDRESS_SIZE_OFFSET // AddressSizeOffset
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},
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{
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{ // BaseAddressRegister
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ACPI_GAS_ID_SYSTEM_MEMORY,
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32,
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0,
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32,
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0xA600000 // USB3.0 SNPS base
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},
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{ // BaseAddressRegister
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ACPI_GAS_ID_SYSTEM_MEMORY,
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32,
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0,
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32,
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0xA600000 // USB3.0 SNPS base
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}
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},
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{
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0xFFFFF, // AddressSize
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0x1000, // AddressSize
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},
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USB_SS_DEVICE_NAME_SPACE_STRING, // NameSpaceString
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{ // OEM Data
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DEBUG_DEVICE_OEM_PORT_USBFN_SYNOPSYS, // Controller type
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0,
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'FIX2',
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2, // Number of writes
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{
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//set HS dev speed
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{
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0, // BaseAddressRegister
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2, // Phase
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0, // Reserved
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0xC700, // Offset
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0xfffffff8, // AndValue
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0x0 // OrValue
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},
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//set ULPI_VBUS_VALID
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{
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0, // BaseAddressRegister
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2, // Phase
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0, // Reserved
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0xf8810, // Offset
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0, // AndValue
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0x10100000 // OrValue
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}
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},
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{
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0, // USB Core Number - Primary (Core 0)
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0, //Reserved
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0, //Reserved
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'USBC' //Signature
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}
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} //end OEM data
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},
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// Device USB SS as KDNET on seconday port (SNPS Controller+ QMP/QUSB2 Phy)
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{
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{
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ACPI_DDI_V2_REVISION, // Revision
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ACPI_DDI_V2_4_OEM_LENGTH, // Length
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ACPI_DDI_V2_2_REGISTER_CNT, // BaseAddressRegisterCount
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sizeof(USB_SS1_DEVICE_NAME_SPACE_STRING), // NameSpaceStringLength
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ACPI_DDI_V2_2_NAMESPACE_STRING_OFFSET, // NameSpaceStringOffset
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sizeof(ACPI_DEBUG_DEVICE_OEM_DATA_V3), // OemDataLength
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ACPI_DDI_V2_2_OEM_DATA_OFFSET, // OemDataOffset
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DEBUG_DEVICE_PORT_TYPE_NET, // PortType
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DEBUG_DEVICE_PORT_SUBTYPE_NET_QCOM, // PortSubtype
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0, // Reserved
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ACPI_DDI_V2_BASE_ADDRESS_REGISTER_OFFSET, // BaseAddressRegisterOffset
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ACPI_DDI_V2_2_ADDRESS_SIZE_OFFSET // AddressSizeOffset
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},
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{
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{ // BaseAddressRegister
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ACPI_GAS_ID_SYSTEM_MEMORY,
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32,
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0,
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32,
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0x0A800000 // USB3.0 SNPS base
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},
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{ // BaseAddressRegister
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ACPI_GAS_ID_SYSTEM_MEMORY,
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32,
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0,
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32,
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0x0A800000 // USB3.0 SNPS base
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}
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},
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{
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0xFFFFF, // AddressSize
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0x1000, // AddressSize
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},
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USB_SS1_DEVICE_NAME_SPACE_STRING, // NameSpaceString
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{ // OEM Data
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DEBUG_DEVICE_OEM_PORT_USBFN_SYNOPSYS, // Controller type
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0,
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'FIX2',
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2, // Number of writes
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{
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//set HS dev speed
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{
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0, // BaseAddressRegister
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2, // Phase
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0, // Reserved
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0xC700, // Offset
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0xfffffff8, // AndValue
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0x0 // OrValue
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},
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//set ULPI_VBUS_VALID
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{
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0, // BaseAddressRegister
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2, // Phase
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0, // Reserved
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0xf8810, // Offset
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0, // AndValue
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0x10100000 // OrValue
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}
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},
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{
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1, // USB Core Number - Primary (Core 1)
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0, //Reserved
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0, //Reserved
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'USBC' //Signature
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}
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} //end OEM data
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}
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};
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