Android/edk2-msm
0
0
Fork 1
mirror of https://github.com/edk2-porting/edk2-msm synced 2025-06-07 17:21:32 +00:00
Code Activity
Files
master
edk2-msm/Silicon/Qualcomm/msm8998/AcpiTables/pep_cpr.asl
Xilin Wu 934a951950 Upload msm8998 files 
for someone else to test, my system seems to be broken
2022-10-14 21:26:10 +08:00

482 lines
12 KiB
C
Executable File
Raw Permalink Blame History

Scope (\_SB.PEP0)
{
Method (CPR4, 0, NotSerialized)
{
Return (CPRF) /* \_SB_.PEP0.CPRF */
}
// CPR data
Name (CPRF, Package (0x08)
{
"CPR_SW_SETTING",
Zero,
Package (0x05)
{
"CPR_CHIP_INFO",
0x0124,
One,
Zero,
Package (0x24)
{
"CPR_SW_CONTROLLER_SETTING",
Zero,
Zero,
"GFX",
One,
Zero,
Zero,
Zero,
0x0C,
0x08,
0x0F,
One,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
0x00017700,
0x0FA0,
0x05061000,
0x1000,
0x00780000,
0x7000,
One,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Package (0x0C)
{
"CPR_SW_LOGIC_AGING",
"Tur_L1",
0x00109A00,
0x1D,
0x00FFFFFF,
Zero,
0x03E8,
0x0654,
One,
0x0F,
0x1C,
One
},
Package (0x08)
{
"CPR_SW_THREAD_SETTING",
Zero,
Zero,
Zero,
0x02,
Zero,
0x02,
Package (0x04)
{
"CPR_SW_CLIENT_SETTING",
"/vdd/gfx",
"GPU",
Zero
}
}
}
},
Package (0x05)
{
"CPR_CHIP_INFO",
0x0124,
0x02,
Zero,
Package (0x24)
{
"CPR_SW_CONTROLLER_SETTING",
Zero,
Zero,
"GFX",
One,
Zero,
Zero,
Zero,
0x0C,
0x08,
0x0F,
One,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
0x00017700,
0x0FA0,
0x05061000,
0x1000,
0x00780000,
0x7000,
One,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Package (0x0C)
{
"CPR_SW_LOGIC_AGING",
"Tur_L1",
0x00109A00,
0x1D,
0x00FFFFFF,
Zero,
0x03E8,
0x0654,
One,
0x0F,
0x1C,
One
},
Package (0x08)
{
"CPR_SW_THREAD_SETTING",
Zero,
Zero,
Zero,
0x02,
Zero,
0x02,
Package (0x04)
{
"CPR_SW_CLIENT_SETTING",
"/vdd/gfx",
"GPU",
Zero
}
}
}
},
Package (0x05)
{
"CPR_CHIP_INFO",
0x0124,
0x02,
One,
Package (0x24)
{
"CPR_SW_CONTROLLER_SETTING",
Zero,
Zero,
"GFX",
One,
Zero,
Zero,
Zero,
0x0C,
0x08,
0x0F,
One,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
0x00017700,
0x0FA0,
0x05061000,
0x1000,
0x00780000,
0x7000,
One,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Package (0x0C)
{
"CPR_SW_LOGIC_AGING",
"Tur_L1",
0x00109A00,
0x1D,
0x00FFFFFF,
Zero,
0x03E8,
0x0654,
One,
0x0F,
0x1C,
One
},
Package (0x08)
{
"CPR_SW_THREAD_SETTING",
Zero,
Zero,
Zero,
0x02,
Zero,
0x02,
Package (0x04)
{
"CPR_SW_CLIENT_SETTING",
"/vdd/gfx",
"GPU",
Zero
}
}
}
},
Package (0x05)
{
"CPR_CHIP_INFO",
0x013F,
One,
Zero,
Package (0x24)
{
"CPR_SW_CONTROLLER_SETTING",
Zero,
Zero,
"GFX",
One,
Zero,
Zero,
Zero,
0x0C,
0x08,
0x0F,
One,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
0x00017700,
0x0FA0,
0x05061000,
0x1000,
0x00780000,
0x7000,
One,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Package (0x0C)
{
"CPR_SW_LOGIC_AGING",
"Tur_L1",
0x00109A00,
0x1D,
0x00FFFFFF,
Zero,
0x03E8,
0x0654,
One,
0x0F,
0x1C,
One
},
Package (0x08)
{
"CPR_SW_THREAD_SETTING",
Zero,
Zero,
Zero,
0x02,
Zero,
0x02,
Package (0x04)
{
"CPR_SW_CLIENT_SETTING",
"/vdd/gfx",
"GPU",
Zero
}
}
}
},
Package (0x05)
{
"CPR_CHIP_INFO",
0x013F,
0x02,
Zero,
Package (0x24)
{
"CPR_SW_CONTROLLER_SETTING",
Zero,
Zero,
"GFX",
One,
Zero,
Zero,
Zero,
0x0C,
0x08,
0x0F,
One,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
0x00017700,
0x0FA0,
0x05061000,
0x1000,
0x00780000,
0x7000,
One,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Package (0x0C)
{
"CPR_SW_LOGIC_AGING",
"Tur_L1",
0x00109A00,
0x1D,
0x00FFFFFF,
Zero,
0x03E8,
0x0654,
One,
0x0F,
0x1C,
One
},
Package (0x08)
{
"CPR_SW_THREAD_SETTING",
Zero,
Zero,
Zero,
0x02,
Zero,
0x02,
Package (0x04)
{
"CPR_SW_CLIENT_SETTING",
"/vdd/gfx",
"GPU",
Zero
}
}
}
},
Package (0x05)
{
"CPR_CHIP_INFO",
0x013F,
0x02,
One,
Package (0x24)
{
"CPR_SW_CONTROLLER_SETTING",
Zero,
Zero,
"GFX",
One,
Zero,
Zero,
Zero,
0x0C,
0x08,
0x0F,
One,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
0x00017700,
0x0FA0,
0x05061000,
0x1000,
0x00780000,
0x7000,
One,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Zero,
Package (0x0C)
{
"CPR_SW_LOGIC_AGING",
"Tur_L1",
0x00109A00,
0x1D,
0x00FFFFFF,
Zero,
0x03E8,
0x0654,
One,
0x0F,
0x1C,
One
},
Package (0x08)
{
"CPR_SW_THREAD_SETTING",
Zero,
Zero,
Zero,
0x02,
Zero,
0x02,
Package (0x04)
{
"CPR_SW_CLIENT_SETTING",
"/vdd/gfx",
"GPU",
Zero
}
}
}
}
})
}
View Git Blame Copy Permalink