mirror of
https://github.com/edk2-porting/edk2-msm
synced 2025-06-03 03:46:33 +00:00
48 lines
3.1 KiB
C
48 lines
3.1 KiB
C
#ifndef UARTQUPV3_H
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#define UARTQUPV3_H
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#define UART_DEBUG_PORT_BASE FixedPcdGet64(PcdDebugUartPortBase)
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#define UART_BASE_ADDR UART_DEBUG_PORT_BASE
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#define RING_SIZE 256
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#define MemWrite(off1,off2,val) (*((volatile UINT32*)(UINTN)(UART_BASE_ADDR+(off1)+(off2)))=((UINT32)(val)))
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#define MemRead(off1,off2,v) ((*((volatile UINT32*)(UINTN)(UART_BASE_ADDR+(off1)+(off2))))&(v))
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#define MemReadMask(off1,k) MemRead(off1,k##_ADDR,k##_MASK)
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#define GENI4_CFG 0x0
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#define GENI4_IMAGE_REGS 0x100
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#define GENI4_DATA 0x600
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#define QUPV3_SE_DMA 0xC00
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#define GENI4_IMAGE 0x1000
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#define GENI_STATUS_ADDR 0x00000040
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#define GENI_S_IRQ_STATUS_ADDR 0x00000040
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#define GENI_RX_FIFO_ADDR 0x00000180
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#define GENI_TX_FIFO_STATUS_ADDR 0x00000200
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#define GENI_RX_FIFO_STATUS_ADDR 0x00000204
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#define SE_HW_PARAM_0_ADDR 0x00000224
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#define GENI_STATUS_MASK 0x1fffff
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#define GENI_S_IRQ_STATUS_MASK 0xfc07f3f
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#define GENI_RX_FIFO_MASK 0xffffffff
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#define GENI_TX_FIFO_STATUS_MASK 0xffffffff
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#define GENI_RX_FIFO_STATUS_MASK 0xffffffff
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#define SE_HW_PARAM_0_MASK 0x3f3f79ff
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#define GENI_M_CMD0_ADDR 0x00000000
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#define GENI_M_IRQ_EN_SET_ADDR 0x0000001c
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#define GENI_M_IRQ_EN_CLEAR_ADDR 0x00000020
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#define GENI_S_IRQ_CLEAR_ADDR 0x00000048
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#define GENI_S_IRQ_EN_SET_ADDR 0x0000004c
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#define GENI_S_IRQ_EN_CLEAR_ADDR 0x00000050
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#define GENI_TX_FIFO_ADDR 0x00000100
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#define UART_TX_TRANS_CFG_ADDR 0x0000015c
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#define GENI_TX_PACKING_CFG0_ADDR 0x00000160
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#define GENI_TX_PACKING_CFG1_ADDR 0x00000164
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#define UART_TX_TRANS_LEN_ADDR 0x00000170
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#define TX_FIFO_WC 0xfffffff
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#define RX_FIFO_WC 0x1ffffff
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#define RX_LAST_IRQ 0x8000000
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#define TX_FIFO_DEPTH_MASK 0x3f0000
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#define TX_FIFO_DEPTH_SHIFT 0x10
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#define TX_FIFO_WATERMARK_IRQ 0x40000000
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#define RX_FIFO_WATERMARK_IRQ 0x4000000
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#define RX_LAST_VALID_BYTES_MASK 0x70000000
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#define RX_LAST_VALID_BYTES_SHIFT 0x1c
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#define M_GENI_CMD_ACTIVE 0x1
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#endif
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